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Commit Graph

92 Commits

Author SHA1 Message Date
0924f8adb0 print out assigned inerrupt ranges 2016-09-29 11:59:32 -07:00
4c3e8ec1b4 assign interrupt ranges deterministically 2016-09-29 11:59:32 -07:00
c45cc76cef Get rid of remaining MemIO code
The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.
2016-09-27 16:28:17 -07:00
3926cb936b rocketchip: add pbus width and AMO With classes (#357) 2016-09-27 15:52:13 -07:00
71a9c78e4b add WidthAdapter from AXI slave to Coreplex TL slave 2016-09-27 12:48:01 -07:00
7d6fb950b6 Give TileLink IDs more sensible names
* Outermost -> MCtoEdge
 * MMIO_Outermost -> MMIOtoEdge

Then the corresponding parameters objects are

 * L1toL2 -> innerParams
 * L2toMC -> outerMemParams
 * L2toMMIO -> outerMMIOParams
 * MCtoEdge -> edgeMemParams
 * MMIOtoEdge -> edgeMMIOParams
2016-09-27 12:48:01 -07:00
8a55521b01 move memory width adapter from coreplex to periphery 2016-09-27 12:48:01 -07:00
e36441a046 use correct parameters object for MMIO width adapter 2016-09-27 12:48:01 -07:00
201e247f73 Factor coreplex IO connection into separate trait (#350)
This would allow, for instance, putting the coreplex on a separate clock
domain and crossing the IOs over through asynchronous queues.

The ExampleMultiClockTop* classes are removed since they no longer fit
into the class hierarchy.
2016-09-27 11:55:32 -07:00
6316ebd58f make naming of L2toMC parameter object consistent between coreplex and periphery 2016-09-26 17:28:21 -07:00
ea9f0a868f TileLink utility objects should not take implicit parameters
We have a handful of TileLink-related helper objects
(wrappers, unwrappers, width adapters, and enqueuers). Previously, using
them could be error-prone, because you had to make sure the implicit
parameters they took in had the same TLId as the TileLinkIO bundles
passed in as inputs. This is rather silly, we should just use the
parameters in the bundle.
2016-09-26 17:28:21 -07:00
dd9558f45d rocketchip: generate GraphML output 2016-09-26 14:35:46 -07:00
14cd39e045 rocketchip: rename identically names devices with _%d (#340)
* rocketchip: rename identically names devices with _%d

If you connect two devices with the same name in TL2 (totally ok there),
when they get put into the TL1 addrmap, one gets silently overwritten.
This renames the second occurance as _1, third as _2, and so on...

* junctions: blow if duplicates add to addrmap
2016-09-26 13:05:49 -07:00
77a0f76289 Cleanup jtag dtm (#342)
* debug: Clean up Debug TransportModule synchronizer

With async reset async queues, I feel its safe/cleaner
to remove the one-off "AsyncMailbox verilog black-box
and use the common primitive.

I also added some comments about correct usage of this
block. Probably the 'TRST' signal should be renamed
to make it less confusing, as it requires some processing
of the real JTAG 'TRST' signal.
2016-09-26 11:10:27 -07:00
d175bb314d Periphery: make bus width and arithmetic atomics configurable (#337) 2016-09-23 15:25:58 -07:00
a421469754 tilelink2: change adapters to use TLAdapter(params, defaults)(node)
This API makes it much more readable when you have multiple adapters
combined into a single line. The arguments for each adapter stay
beside the adapter.

For example, this:
  peripheryBus.node := TLWidthWidget(TLBuffer(TLAtomicAutomata()(TLHintHandler(legacy.node))), legacy.tlDataBytes)
becomes this:
  peripheryBus.node := TLWidthWidget(legacy.tlDataBytes)(TLBuffer()(TLAtomicAutomata()(TLHintHandler()(legacy.node))))
2016-09-22 20:52:46 -07:00
22053289ef fix typo rv64iu -> rv64ui 2016-09-22 17:33:35 -07:00
673efb400d Merge branch 'master' into unittest-config 2016-09-22 16:20:53 -07:00
1e54820f8c Merge remote-tracking branch 'origin/master' into unittest-config 2016-09-22 16:03:51 -07:00
411ee378de Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages. 2016-09-22 15:59:29 -07:00
0a3718881f rocketchip: re-enable testing of atomics 2016-09-22 15:18:54 -07:00
83c08a931d [WIP] Generators for unittest and groundtest; disambiguate groundtest.TrafficGenerator 2016-09-22 14:57:18 -07:00
47c5d1a992 [WIP] Move RocketTestSuite generation into RocketchipGenerator 2016-09-22 14:31:45 -07:00
1b1ef3be07 simplify base Coreplex bundle 2016-09-21 18:29:28 -07:00
d2df6397cd rename trc (tile reset clock) bundles to tcr (tile clock reset) 2016-09-21 18:29:28 -07:00
5bb575ef74 rename internal/external MMIO network to cbus/pbus respectively 2016-09-21 18:29:28 -07:00
7afd630d3e add multiclock support to Coreplex 2016-09-21 16:55:26 -07:00
ed91e9a89b Merge remote-tracking branch 'origin' into testharness-refactor 2016-09-20 13:03:21 -07:00
b97a0947a9 [rocketchip] enable piecewise Generator output 2016-09-20 12:57:56 -07:00
3b38736a8e Make BaseTopModule and BaseTopModule abstract
They aren't meant to be directly instantiated.
2016-09-19 17:18:35 -07:00
d0572d6aab Allow reset vector to be set dynamically
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins.  Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.

Additionally, allow MTVEC to *not* be reset.  In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does.  So the reset value is superfluous.
2016-09-19 17:18:03 -07:00
df442ed82c [rocketchip] avoid pending merge conflict] 2016-09-19 13:24:01 -07:00
ddcf1b4099 Use PROJECT rather than MODEL in name of binary and generated src files. 2016-09-19 13:23:17 -07:00
7b8aa6c839 [rocketchip] split out Base and Example tops 2016-09-19 11:00:13 -07:00
76d8ed6a69 tilelink2: remove 'strided'; !contiguous is clearer 2016-09-17 16:14:25 -07:00
01c1886b9d Utils: cacheable only if there is a cache manager 2016-09-17 00:56:21 -07:00
c70045b8b3 Utils: express cacheability from TL2 to TL1 2016-09-17 00:16:40 -07:00
e3d2bd3323 Top: print memory region properties, RWX [C] 2016-09-17 00:16:00 -07:00
5c858685aa Utils: support managers with multiple addresses 2016-09-16 18:03:49 -07:00
a9382b3116 Periphery: test bench looks for "testram" 2016-09-16 17:47:20 -07:00
b5ce6150c7 Periphery: dynamically create address map + config string for TL2 2016-09-16 17:28:47 -07:00
63f13ae7ce Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor 2016-09-16 17:10:52 -07:00
86b70c8c59 Rename PRCI to CoreplexLocalInterrupter
That's all it's doing (there wasn't much PRC).
2016-09-16 14:26:34 -07:00
e1d7f6d7df PRCI: always use bus width >= XLen 2016-09-15 22:15:07 -07:00
fb24e847fd rocketchip: globals are for sissies 2016-09-15 21:28:56 -07:00
644f8fe974 rocketchip: switch to TL2 mmio + port PRCI 2016-09-15 21:28:56 -07:00
f2fe437fa4 Use CDEMatchError for improved performance (#304) 2016-09-15 19:47:18 -07:00
245f8ab76b [util] move LatencyPipe into util 2016-09-15 13:30:34 -07:00
be9ddae77f make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs 2016-09-15 13:04:01 -07:00
c6f252a913 Remove Option from success flag in coreplex; just use a sane default. 2016-09-15 12:19:22 -07:00