riscv/rocket-chip
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d2df6397cd
rocket-chip/src/main/scala/rocketchip
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Yunsup Lee d2df6397cd rename trc (tile reset clock) bundles to tcr (tile clock reset)
2016-09-21 18:29:28 -07:00
..
BaseTop.scala rename internal/external MMIO network to cbus/pbus respectively 2016-09-21 18:29:28 -07:00
Configs.scala add multiclock support to Coreplex 2016-09-21 16:55:26 -07:00
DebugTransport.scala junctions: refactor the Crossing type 2016-09-13 15:51:18 -07:00
ExampleTop.scala rename trc (tile reset clock) bundles to tcr (tile clock reset) 2016-09-21 18:29:28 -07:00
Generator.scala [rocketchip] enable piecewise Generator output 2016-09-20 12:57:56 -07:00
Periphery.scala rename internal/external MMIO network to cbus/pbus respectively 2016-09-21 18:29:28 -07:00
TestHarness.scala Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor 2016-09-16 17:10:52 -07:00
Utils.scala rename internal/external MMIO network to cbus/pbus respectively 2016-09-21 18:29:28 -07:00