Wesley W. Terpstra c70045b8b3 Utils: express cacheability from TL2 to TL1

2016-09-17 00:16:40 -07:00

..

Configs.scala

rocketchip: globals are for sissies

2016-09-15 21:28:56 -07:00

DebugTransport.scala

junctions: refactor the Crossing type

2016-09-13 15:51:18 -07:00

Generator.scala

rocketchip: globals are for sissies

2016-09-15 21:28:56 -07:00

Periphery.scala

Periphery: test bench looks for "testram"

2016-09-16 17:47:20 -07:00

TestConfigs.scala

rocketchip: globals are for sissies

2016-09-15 21:28:56 -07:00

TestHarness.scala

rocketchip: globals are for sissies

2016-09-15 21:28:56 -07:00

Top.scala

Top: print memory region properties, RWX [C]

2016-09-17 00:16:00 -07:00

UnitTest.scala

rocketchip: globals are for sissies

2016-09-15 21:28:56 -07:00

Utils.scala

Utils: express cacheability from TL2 to TL1

2016-09-17 00:16:40 -07:00