riscv/rocket-chip
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Author SHA1 Message Date
Henry Cook
05112b49a3 Merge branch 'master' into tl-error 2017-09-27 14:50:17 -07:00
Henry Cook
652d57291c Merge pull request #1018 from freechipsproject/refine-trace-port 
Separate interrupt bit from cause field in trace bundle
 2017-09-27 14:46:27 -07:00
Henry Cook
5d08b37dab Merge pull request #1019 from freechipsproject/move-rocket-int-sync 
Move rocket output interrupt syncronizers
 2017-09-27 14:46:02 -07:00
Henry Cook
f48bf2ac2f rocket: connect uncrossed output interrupts 2017-09-27 12:53:19 -07:00
Andrew Waterman
78f3877e02 Trace tval field should be zero when not taking exceptions 2017-09-27 12:51:10 -07:00
Andrew Waterman
583adeee88 Separate interrupt bit from cause field in trace bundle 2017-09-27 12:41:30 -07:00
Wesley W. Terpstra
1fda05970a rocket: move interrupt synchronizers to correct side of crossing 2017-09-27 12:33:08 -07:00
Henry Cook
45d26ea130 Merge pull request #1015 from freechipsproject/coherence-manager 
coreplex: clean up coherence manager attachment point
 2017-09-26 11:09:48 -07:00
Henry Cook
9d5e96672e coreplex: clean up coherence manager attachment point 2017-09-25 18:07:51 -07:00
pbing
a86a9c5564 Fix omitted parameter (#1014) 2017-09-25 14:11:28 -07:00
Henry Cook
5662d1de0b Merge pull request #1012 from freechipsproject/halt-and-catch-fire 
Halt and Catch Fire
 2017-09-22 09:30:30 -07:00
Henry Cook
81e136aa37 rocket: give l2 tlb a nice name 2017-09-21 18:13:39 -07:00
Henry Cook
30c8c8c517 Revert "try to give seqmems clearer names" 
This reverts commit 8db5bbbae0.

This attempt at clarification instead results in confusing generated verilog like:
`dcache_data_arrays_0 icache_data_arrays_0 (...);`
because of deduplication of identically dimensioned SRAMs...
 2017-09-21 18:02:32 -07:00
Henry Cook
e0b9f9213a make halt_and_catch_fire Optional 2017-09-21 14:58:47 -07:00
Henry Cook
28b635e721 tile: add halt_and_catch_fire signal 
for unrecoverable / fatal errors
 2017-09-21 14:58:47 -07:00
Henry Cook
a887baa615 rocket: base trait for reporting ecc errors 2017-09-21 14:58:47 -07:00
Megan Wachs
ffa3ab29ac Merge pull request #1006 from freechipsproject/async_reset_reg 
async_reset_reg: Don't randomize the register if rst is asserted anyway
 2017-09-21 11:48:04 -07:00
Jim Lawson
4f58aab26f Bumpplugins - add sbt-coverage (#1004) 
Don't advance to plugin versions that are incompatible with current chisel3 code.
 2017-09-20 17:17:55 -07:00
Andrew Waterman
88c782cc70 Report D$ uncorrectable errors on C channel 2017-09-20 17:15:11 -07:00
Andrew Waterman
6bc20942b5 Don't cache TL error responses; report access exceptions 2017-09-20 17:01:08 -07:00
Henry Cook
323a207bdd Merge pull request #1005 from freechipsproject/trace 
Rename trace.addr -> iaddr
 2017-09-20 15:34:45 -07:00
Andrew Waterman
9b828a2640 Only look at error signal on last beat 2017-09-20 15:15:21 -07:00
Megan Wachs
cda89fbacb async_reset_reg: Don't randomize the register if rst is asserted anyway 2017-09-20 14:47:00 -07:00
Andrew Waterman
026fa14bf8 Rename trace.addr -> iaddr 2017-09-20 14:32:41 -07:00
Henry Cook
1cb91eed41 Merge pull request #1003 from freechipsproject/ma-fetch 
Don't write badaddr on misaligned fetch exceptions
 2017-09-20 14:28:26 -07:00
Andrew Waterman
5b2f458214 Merge branch 'master' into ma-fetch 2017-09-20 12:18:03 -07:00
Andrew Waterman
f1a506476b Merge pull request #994 from freechipsproject/beu 
Add L1 bus-error unit
 2017-09-20 12:17:08 -07:00
Henry Cook
00cf089350 Merge pull request #1002 from freechipsproject/trace 
Add instruction-trace port
 2017-09-20 11:50:40 -07:00
Andrew Waterman
f5bd639863 Don't write badaddr on misaligned fetch exceptions 
It's optional, and we were doing it wrong before, so just don't do it.
 2017-09-20 10:52:41 -07:00
Andrew Waterman
db57e943f3 Report TL errors into D$ 2017-09-20 00:05:07 -07:00
Andrew Waterman
aaad73f019 Add an intra-tile xbar 2017-09-20 00:05:07 -07:00
Andrew Waterman
afad25fceb Integrate L1 BusErrorUnit 2017-09-20 00:05:07 -07:00
Andrew Waterman
dbf599f6a1 Support SynchronizerShiftReg(sync = 0) 
This makes it easier to parameterize code where the synchronizer
might not always be needed.
 2017-09-20 00:05:07 -07:00
Andrew Waterman
79dab487fc Implement bus error unit 2017-09-20 00:05:07 -07:00
Andrew Waterman
ed18acaae0 Report D$ errors 2017-09-20 00:05:07 -07:00
Andrew Waterman
034ea722f4 Report I$ errors 2017-09-20 00:05:07 -07:00
Andrew Waterman
9a175b0fb1 Statically report error correction/detection capability from ECC codes 2017-09-20 00:05:07 -07:00
Andrew Waterman
4d6d6ff641 Add instruction-trace port 2017-09-19 22:59:57 -07:00
Andrew Waterman
acea94bcef Merge pull request #1001 from freechipsproject/address-decoder 
Address decoder "improvements"
 2017-09-19 22:38:53 -07:00
Jacob Chang
b4fc5104d4 Add cover property API that can be refined through Config PropertyLibrary (#998) 2017-09-19 19:26:54 -07:00
Henry Cook
57e8fe0a6b Merge pull request #1000 from freechipsproject/name-seqmems 
try to give seqmems clearer names for use with external tools
 2017-09-19 17:59:00 -07:00
Andrew Waterman
87b92cb206 Scan AddressDecoder bits left to right 
This heuristic is brittle but fixes deduplication in RocketTile.
 2017-09-19 17:47:24 -07:00
Andrew Waterman
72bd89a2af Add another AddressDecoder debug message 2017-09-19 17:47:17 -07:00
Andrew Waterman
fb2ad11347 Improve AddressDecoder optimization function 
This function is better 27% of the time but worse 6% of the time.
 2017-09-19 17:47:12 -07:00
Henry Cook
8db5bbbae0 try to give seqmems clearer names 2017-09-19 13:41:11 -07:00
Megan Wachs
cbd65cd247 Merge pull request #992 from freechipsproject/test_mode_reset 
reset_catch: Allow Test Mode Overrides
 2017-09-18 14:16:49 -07:00
pbing
528deefdc7 Change SystemVerilog statement into standard Verilog (#997) 2017-09-18 10:57:07 -07:00
Megan Wachs
826fc8ba61 Merge remote-tracking branch 'origin/master' into test_mode_reset 2017-09-18 09:50:27 -07:00
Yunsup Lee
c24b275fd9 Merge pull request #996 from freechipsproject/fix-dcache-bug 
Only merge stores that aren't yet pending
 2017-09-17 15:59:32 -07:00
Andrew Waterman
d93d7b9fa4 Only merge stores that aren't yet pending 
This fixes a deadlock (and possibly memory corruption, though that is
unconfirmed).  The following sequence manifests it, assuming t0
is 32-byte aligned:

    sw t0, 0(t0)
    sw t0, 16(t0)
    lw t1, 4(t0)
    lw t2, 4(t0)
 2017-09-17 15:01:07 -07:00