891 Commits

Author	SHA1	Message	Date
Henry Cook	c06cbf523b	Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore.	2013-05-23 15:26:20 -07:00
Henry Cook	6a69d7d7b5	pass closure to generate bank addr	2013-05-23 14:58:19 -07:00
Andrew Waterman	d825c9d6e9	make fpga Makefile work with updated Makefrag	2013-05-02 05:09:45 -07:00
Andrew Waterman	cfa86dba4f	add FPGA test bench ... The memory models now support back pressure on the response.	2013-05-02 04:59:32 -07:00
Andrew Waterman	50bd9a08a7	resynchronize fpga uncore	2013-05-01 01:12:47 -07:00
Yunsup Lee	93df795e48	change LLC leaf SRAM size	2013-04-22 11:06:50 -07:00
Huy Vo	2ac3fd5306	get rid of init_node	2013-04-20 01:36:32 -07:00
Huy Vo	0d87e3bacc	fixed init pin generation	2013-04-20 00:38:01 -07:00
Henry Cook	a01cdf95fd	tell physical networks carring cache lines to lock arbitration for REFILL_CYCLES pumps	2013-04-10 13:53:27 -07:00
Henry Cook	16ad8a7e9c	Fixes after merge	2013-03-25 19:14:38 -07:00
Andrew Waterman	8e926f8d79	remove aborts	2013-03-25 17:01:46 -07:00
Henry Cook	eec590c1bf	Added support for multiple L2 banks. Moved tile IO queueing.	2013-03-25 17:01:46 -07:00
Henry Cook	806f897fc4	nTiles -> nClients in LogicalNetworkConfig	2013-03-25 17:01:46 -07:00
Andrew Waterman	ce4c1aa566	remove aborts	2013-03-25 17:01:46 -07:00
Henry Cook	cf76665d09	writebacks on release network pass asm tests and bmarks	2013-03-25 17:01:46 -07:00
Henry Cook	a0dc8d52d6	using new network and l2 controller	2013-03-25 17:01:46 -07:00
Yunsup Lee	9efe71412f	add DRAMSideLLCNull	2013-03-19 00:43:34 -07:00
Andrew Waterman	4077b22929	include fesvr as a library; improve harnesses	2013-01-24 23:57:23 -08:00
Yunsup Lee	516a64f576	commit vec=true	2013-01-22 20:24:33 -08:00
Henry Cook	bb5c465bb3	Switched back to old, better-tested hub on master	2013-01-22 19:57:31 -08:00
Henry Cook	5b82d72eb7	New TileLink bundle names	2013-01-21 17:19:07 -08:00
Henry Cook	72bba81a76	now using single-ported coherence master	2013-01-16 23:58:24 -08:00
Henry Cook	e33648532b	Refactored packet headers/payloads	2013-01-15 15:57:06 -08:00
Henry Cook	a922b60152	Merge branch 'master' of github.com:ucb-bar/reference-chip into network-refactor	2013-01-07 14:23:49 -08:00
Henry Cook	f2cef8d8d2	new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore	2013-01-07 14:19:55 -08:00
Andrew Waterman	fd727bf8aa	add some of the zedboard fpga infrastructure ... you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness for VCS simulation yet.	2013-01-06 03:58:10 -08:00
Henry Cook	d0805359a5	Refactored uncore conf	2012-12-13 11:46:29 -08:00
Henry Cook	1d7f1a8182	Removed dummy tile instances	2012-12-12 16:44:03 -08:00
Henry Cook	0e73cc8c12	Removed dummy tile instances	2012-12-12 16:41:21 -08:00
Henry Cook	177909c955	Initial version of phys/log network compiles	2012-12-12 11:15:10 -08:00
Henry Cook	be4e5b8327	Initial version of phys/log network compiles	2012-12-12 00:06:14 -08:00
Andrew Waterman	e12af07722	update to newest rocket	2012-11-25 04:40:46 -08:00
Yunsup Lee	4d73e6e38a	revamp vector yet again with new D$	2012-11-18 03:14:22 -08:00
Andrew Waterman	b58214d7e3	remove more global constants	2012-11-17 17:25:43 -08:00
Andrew Waterman	e2afae011a	factor out global constants	2012-11-06 08:18:40 -08:00
Andrew Waterman	0c372fc9ec	refactor I$ config into RocketConfiguration	2012-11-04 17:00:19 -08:00
Henry Cook	538b23c223	Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles	2012-10-23 12:52:59 -07:00
Yunsup Lee	3edc1f42aa	revamp the backup memory link in the vlsi backend	2012-10-23 03:31:34 -07:00
Andrew Waterman	367b5489d1	first crack at continuous compilation/testing flow ... try it out: cd emulator; make test	2012-10-19 04:09:07 -07:00
Andrew Waterman	edf0eeed01	integrate updated rocket/uncore	2012-10-18 17:51:41 -07:00
Huy Vo	24a49350cc	reference chip design	2012-10-09 13:05:56 -07:00