Andrew Waterman fd727bf8aa add some of the zedboard fpga infrastructure ... you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness for VCS simulation yet.		2013-01-06 03:58:10 -08:00
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scala	add some of the zedboard fpga infrastructure	2013-01-06 03:58:10 -08:00