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Commit Graph

5547 Commits

Author SHA1 Message Date
030c6f0206 subsystem: bus wrappers now in BaseSubsystem 2018-02-21 14:52:59 -08:00
b617e26c13 util: augment String and use to name couplers 2018-02-21 14:43:47 -08:00
a6d3965491 tilelink: bus wrapper scopes called 'couplers' 2018-02-21 14:43:47 -08:00
57edd7facf subsystem: streamline toTile and fromTile attachment 2018-02-21 14:43:47 -08:00
ef3addee7b diplomacy: put full module + instance path into graphml Description 2018-02-21 14:43:47 -08:00
62aee56807 diplomacy: base instance names on ValName and module names on className 2018-02-21 14:43:47 -08:00
3f436a7612 subsystem: new bus attachment api 2018-02-21 14:43:47 -08:00
8462ea3d5b coreplex => subsystem 2018-02-21 14:42:24 -08:00
32c5c3c04d Merge pull request #1245 from freechipsproject/rv32d
Support fLen > xLen
2018-02-21 11:05:44 -08:00
8998a97ea1 Preserve WithRV32 behavior: FLEN = 32 2018-02-20 18:28:47 -08:00
1dc1e2c099 support testing RV32D configs 2018-02-20 16:16:39 -08:00
d4fb7ad6a2 DefaultRV32Config should provide fdiv/fsqrt
This is a holdover from before we had built the functional unit.
2018-02-20 16:16:39 -08:00
b487448961 Add FPUParams.fLen option, decoupled from xLen 2018-02-20 16:16:39 -08:00
5e35015651 Minor Rocket fixes to support fLen != xLen 2018-02-20 16:16:39 -08:00
bd29184e11 debug: get beatBytes from pbus, not XLen 2018-02-20 16:16:39 -08:00
62f9b84439 plic: get beatBytes from pbus, not XLen 2018-02-20 16:16:39 -08:00
52e22a1dd8 clint: get beatBytes from pbus, not XLen 2018-02-20 16:16:39 -08:00
1b158d2caf Merge pull request #1244 from freechipsproject/dtim-priority
Give Rocket priority over DTIM TL port
2018-02-20 14:19:21 -08:00
1bac2cbdf8 Give Rocket priority over DTIM TL port
The TL port can easily starve the processor, even at only 20% utilization,
because of a bad interaction with the pipeline.  Giving the processor
static priority is OK in practice, since <50% of instructions are loads
and stores in typical workloads.  Even if it executes 100% loads and stores,
it must eventually encounter an I$ miss, taken branch, or exception, so
even malicious code can't permanently starve the TL port.
2018-02-20 11:23:10 -08:00
db35f45bf7 Merge pull request #1242 from freechipsproject/unnamed_reg_fix
RegFieldDesc: fix the output produced for undescribed registers
2018-02-16 14:27:53 -08:00
135f06cefc Clarify errors, init jtag error code to zero (#1241)
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-02-16 13:03:51 -08:00
5affd3bec2 RegFieldDesc: fix the output produced for undescribed registers 2018-02-16 10:24:12 -08:00
cf7cd03d64 Merge pull request #1239 from freechipsproject/reduce_debug_flags
Reduce Debug Module "flags"
2018-02-16 08:53:41 -08:00
bb1976552f Merge pull request #1238 from freechipsproject/error-bifurcate
Error: don't be an exception wrt. caching
2018-02-15 22:19:27 -08:00
d72abb7a12 Debug: revert change to how flags are named 2018-02-15 21:49:32 -08:00
dcfbdabe60 CacheCork: better document edge conditions 2018-02-15 19:14:30 -08:00
ecd069dca4 tilelink: allow FIFO caches
Probably not a smart thing to build, but not illegal!
2018-02-15 19:09:37 -08:00
acecc407a5 HellaCache: we do NOT really support probe below the block size!
If we did, you would somehow have to retain ownership of the
unprobed parts of the block, in case they happened to be dirty.
2018-02-15 19:08:43 -08:00
c34b940d9a ElaborationArtefacts: revert unintentional change 2018-02-15 14:23:54 -08:00
e0c3b22d61 RegFieldDesc: same string used to insert/compare 2018-02-15 14:23:27 -08:00
b95f68447f RegFieldDesc: Prevent different RegField JSONS from overwriting eachother. 2018-02-15 14:01:47 -08:00
64d3731e45 RegFieldDesc: don't put characters into names that need to be sanitized 2018-02-15 13:25:06 -08:00
197699b93a Debug: don't need to fully populate flags array 2018-02-15 13:23:51 -08:00
fa412246b3 Error: don't be an exception wrt. caching
Prior to this PR, the error device was allowed to be cached by
multiple actors despite never probing any of them. This is a
pretty unusual set of properties that has caused us trouble
several times now in the past.

Let's instead put the Error device into one of two very well
established categories: a straight-up MMIO device or a tracked
memory region.
2018-02-14 23:02:55 -08:00
e2e678d53d Merge pull request #1183 from freechipsproject/regfield_descriptions
more detailed RegField descriptions
2018-02-12 14:25:06 -08:00
6f70d25ef9 Merge pull request #1184 from freechipsproject/regfield_json
TLRegMapper: emit a JSON file describing the register fields
2018-02-12 12:00:01 -08:00
de91672e9a RegFieldDesc: simplify the output RegFieldDesc JSON to just a list of reg fields 2018-02-12 08:32:52 -08:00
7bf0121f07 PLIC: correct some descriptions 2018-02-12 08:31:29 -08:00
08acbe1a29 RegFieldDesc: Clean up both descriptions and JSON presentations 2018-02-11 23:57:57 -08:00
5ab4204e8a RegField: the JSON will just leave things out of type None 2018-02-11 22:51:36 -08:00
3b44f380d8 TLRegMapper: emit a JSON file describing the register fields 2018-02-11 22:51:36 -08:00
256f8ffc6b Clint: Annotate regmap with RegFieldDesc 2018-02-11 21:33:09 -08:00
718c88a8f9 PLIC: Annotate regmap with RegFieldDescs 2018-02-11 21:05:17 -08:00
13b120fb01 Debug: Annotate regmaps with RegFieldDescs 2018-02-10 20:11:24 -08:00
7abf6e1c8a RegMapper: Update cover props to use new RegFieldDesc objects 2018-02-10 13:17:38 -08:00
4ab1585a78 Register Field: Add a more verbose description object
Add versions of the RegField functions to take it in, and
update Example device to use it.
2018-02-10 13:17:18 -08:00
1bfdfacda0 Merge pull request #1234 from grebe/bindFixup
Use bind from global namespace
2018-02-09 15:59:51 -08:00
ac62bf7f22 Use bind from global namespace 2018-02-09 14:16:20 -08:00
9a56221566 Merge pull request #1192 from seldridge/auto-plusargs
Automatic PlusArg for emulator.cc
2018-02-08 18:29:31 -08:00
fe277cf6f0 Merge branch 'master' into auto-plusargs 2018-02-06 18:38:44 -08:00