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Author SHA1 Message Date
Andrew Waterman 4cfae27efd
Implement Hauser misa.C misalignment proposal (#1301)
See 0472bcdd16

- Reads of xEPC[1] are masked when RVC is disabled
- Writes to MISA are suppressed if they would cause a misaligned fetch
- Misaligned PCs no longer need to be checked in decode
2018-03-21 23:42:01 -07:00
Henry Cook 70895b6ffa rocket: make RocketTileParams trivial to serialize
By storing ECC setting as Option[String] and converting it
to a scala Code class later.
2018-03-20 11:25:02 -07:00
Andrew Waterman d6bc9c53f0
Save a little power during reset by not writing D$ tags (#1287) 2018-03-15 19:23:09 -05:00
Henry Cook ea89259dd4 RegFieldDesc: reserved omits () 2018-03-12 08:24:36 -07:00
Megan Wachs 15e058e3da RegFieldDesc: change how reserved is indicated 2018-03-12 08:24:36 -07:00
Megan Wachs d889a0ca16 RegFieldDesc: add volatile to cause reg in BUE 2018-03-12 08:24:36 -07:00
Megan Wachs 7458378a4a RegFieldDesc: Update reg field descs to be more correct for devices. 2018-03-12 08:24:36 -07:00
Megan Wachs e3be5db3e6 BUE: more verbose register descriptions 2018-03-05 12:02:42 -08:00
Andrew Waterman 644ba6dafa Add BusErrorUnit RegFieldDesc 2018-03-02 17:25:13 -08:00
Jack Koenig 8c6e745653
Bump chisel and firrtl (#1232)
* Misc changes to better enable autoclonetype
* Bump chisel3 and firrtl and SBT to 1.1.1
2018-03-01 15:19:12 -08:00
Henry Cook 20a8876856
Merge pull request #1190 from freechipsproject/bus-api
BusWrapper API Update
2018-03-01 01:13:50 -08:00
Andrew Waterman eb6e192ec0 Fix mapping of acquire/release AMOs to fence operations
AMO.aq should be implemented as AMO;FENCE, whereas AMO.rl should be
implemented as FENCE;AMO.  These had been swapped.  This error does
not affect cacheable accesses using the blocking D$, nor does it
affect accesses to the data scratchpad, nor does it affect accesses
to strongly ordered I/O regions (which is the default).

Cacheable accesses using the nonblocking D$ and accesses to weakly
ordered I/O regions may manifest memory-ordering violations.  For
these accesses, the workaround is to use AMO.aqrl whenever AMO.aq
or AMO.rl had been used.
2018-02-23 16:39:47 -08:00
Andrew Waterman aad75f2285 Implement misa.C proposal
This proposal hasn't been adopted yet, but anything is better than the
current implementation, where clearing misa.C when the PC is misaligned
is effectively undefined.
2018-02-22 15:12:19 -08:00
Andrew Waterman c1ee31d133 Fix debug trigger point for stores
In Rocket, debug triggers are supposed to happen before a store
occurs, rather than after.  Previously, we reported the exception
on the store's PC, but the store occurred anyway.  This probably
hasn't been problematic in practice because most stores are
idempotent.
2018-02-22 14:56:57 -08:00
Henry Cook 8462ea3d5b coreplex => subsystem 2018-02-21 14:42:24 -08:00
Andrew Waterman b487448961 Add FPUParams.fLen option, decoupled from xLen 2018-02-20 16:16:39 -08:00
Andrew Waterman 5e35015651 Minor Rocket fixes to support fLen != xLen 2018-02-20 16:16:39 -08:00
Wesley W. Terpstra acecc407a5 HellaCache: we do NOT really support probe below the block size!
If we did, you would somehow have to retain ownership of the
unprobed parts of the block, in case they happened to be dirty.
2018-02-15 19:08:43 -08:00
Henry Cook fe277cf6f0
Merge branch 'master' into auto-plusargs 2018-02-06 18:38:44 -08:00
Andrew Waterman efc6c9cbd3 Let user of CSRFile decide when to set tval
I also renamed badaddr to tval (the correct name).
2018-02-06 14:05:03 -08:00
Andrew Waterman a59fc3bdaa Teach MulDiv to do either mul-only or div-only by setting unroll=0 2018-02-06 14:03:17 -08:00
Andrew Waterman 69441930b5 Rationalize ALU function encoding
MULHSU and MULHU should match their ISA funct3 encodings to slightly
reduce HW cost.
2018-02-06 14:00:37 -08:00
solomatnikov 5294523551
Keep io.cpu.s1_data for visibility (#1218) 2018-01-31 14:31:42 -08:00
Jacob Chang f4853c4f63
Add cover properties to Core CSRs (#1212) 2018-01-30 00:01:19 -08:00
Andrew Waterman b5ff853e86
Sign-extend the depc CSR (#1209) 2018-01-26 12:07:33 -08:00
Andrew Waterman 8d8e4e1399
Merge pull request #1196 from freechipsproject/interrupt-cover
Cover all exceptions and interrupts
2018-01-25 18:06:13 -08:00
Andrew Waterman d2399b6d0e Cover all exceptions and interrupts 2018-01-25 16:14:56 -08:00
Andrew Waterman a2ca82f92c Add VM covers 2018-01-23 16:13:35 -08:00
Henry Cook 24c1235500 rocket: add address to tlb permissions require msgs 2018-01-18 10:31:51 -08:00
Schuyler Eldridge 355d3b15e8 Merge 'origin/master' into auto-plusargs 2018-01-16 15:45:53 -05:00
Jacob Chang 80ca018e3a
Add cover points for BusErrorUnit (#1193) 2018-01-15 18:00:29 -08:00
Schuyler Eldridge e52d52ae99 Link PlusArg to emulator command line options
- adds a mutable singleton (PlusArgArtefacts) to store information
  about Rocket PlusArgs
- adds methods to PlusArgArtefacts to emit C snippets that are
  consumed by emulator.cc for correct argument parsing and help text
  generation
- emits snippets in $(CONFIG).plusArgs via BaseCoreplex-set
  ElaborationArtefacts
- modify emulator/Makefrag-verilator to include $(CONFIG).plusArgs
- cleanup help text (docstring) for existing PlusArgs

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 14:32:55 -05:00
Henry Cook f5211765e9
Merge pull request #1177 from freechipsproject/dont-touch-2
Make more use of chisel3.experimental.DontTouch
2018-01-09 15:13:55 -08:00
pentin-as c152962642 Dual-port RAM replaced with single-port RAM for tag_array in HellaCache (#1181)
In accordance with https://github.com/freechipsproject/chisel3/issues/752
2018-01-09 13:06:43 -08:00
Andrew Waterman ad0b9a0b1b Reduce cases in which FENCE.I must flush D$
Memory regions that are uncacheable or have get/put effects should not
reside in the D$, so there is no need to flush them.
2018-01-05 13:58:14 -08:00
Henry Cook 4853d1355f rocket: dontTouch HellaCache.io.cpu.resp 2018-01-05 12:50:24 -08:00
Andrew Waterman 206892899f
Merge pull request #1171 from freechipsproject/fix-msb-check
Enforce physical-address canonicalization
2018-01-03 12:06:18 -08:00
Andrew Waterman ee1a9485df Enforce physical-address canonicalization
When xLen > paddrBits, enforce that physical addresses are zero-extended.
This works by checking that the _virtual_ address is _sign_-extended, then
checking that its sign is positive.
2018-01-02 18:47:30 -08:00
Andrew Waterman 7c9a1b0265 Correctly check for virtual-address canonicalization
The previous check was necessary but not sufficient.
2018-01-02 18:41:25 -08:00
Henry Cook b0e1bc3071 tile: cake reduction
* merge HasScratchpadSlavePort into RocketTile
* merge CanHaveSharedFPUModule into BaseTileModule
2018-01-02 17:49:08 -08:00
Henry Cook efe7165b54 tile: BaseTile refactor, pt 2
* 2 layer cake
* no more bundle traits, only call to IO
2018-01-02 15:37:31 -08:00
Henry Cook 1cd018546c tile: BaseTile refactor, pt 1
* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
2017-12-26 11:04:15 -08:00
Henry Cook 895c4b9261
Revert "ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144)" (#1162)
This reverts commit a542ae687e.
2017-12-19 12:16:26 -08:00
Jacob Chang 09160d0cd5
Changed label for DCache and ICache error covers + take away exclusio… (#1155)
* Changed label for DCache and ICache error covers + take away exclusion that shouldn't be there

* rocket: add d-channel error to I$
2017-12-13 20:16:36 -08:00
Wesley W. Terpstra a542ae687e
ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144) 2017-12-08 17:35:14 -08:00
Andrew Waterman 676110bc1f Add cover for a1ebe6da4d 2017-12-07 21:03:42 -08:00
Andrew Waterman a1ebe6da4d Prevent frontend deadlock fetching from uncacheable memory
After detecting a corrupted BTB, don't speculatively update it until
the next non-speculative fetch.  This prevents the frontend from replaying
forever.
2017-12-07 18:56:06 -08:00
Jacob Chang ec3789b365
Add Cross Cover Property Library (#1149)
Add cover points related to memory error to I/D Cache
2017-12-07 18:46:10 -08:00
Andrew Waterman 5c204f98d5
When writing full words to ITIM, ECC errors are correctable (#1148)
* When writing full words to ITIM, ECC errors are correctable

* Disable D$ tag reset state machine when using scratchpad
2017-12-07 16:00:26 -08:00
Richard Xia 50de991f18 Fix typo in breakpoint cover property. 2017-12-04 14:04:24 -08:00