diplomacy: provide a val name for all LazyModule constructions

src/main/scala/amba/ahb/ToTL.scala

@@ -138,5 +138,9 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
 
 object AHBToTL
 {
-  def apply()(implicit p: Parameters) = LazyModule(new AHBToTL).node
+  def apply()(implicit p: Parameters) =
+  {
+    val ahb2tl = LazyModule(new AHBToTL)
+    ahb2tl.node
+  }
 }

src/main/scala/amba/axi4/AsyncCrossing.scala

@@ -43,12 +43,18 @@ class AXI4AsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameter
 
 object AXI4AsyncCrossingSource
 {
-  def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new AXI4AsyncCrossingSource(sync)).node
+  def apply(sync: Int = 3)(implicit p: Parameters) = {
+    val axi4asource = LazyModule(new AXI4AsyncCrossingSource(sync))
+    axi4asource.node
+  }
 }
 
 object AXI4AsyncCrossingSink
 {
-  def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) = LazyModule(new AXI4AsyncCrossingSink(depth, sync)).node
+  def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) = {
+    val axi4asink = LazyModule(new AXI4AsyncCrossingSink(depth, sync))
+    axi4asink.node
+  }
 }
 
 @deprecated("AXI4AsyncCrossing is fragile. Use AXI4AsyncCrossingSource and AXI4AsyncCrossingSink", "rocket-chip 1.2")
@@ -99,5 +105,6 @@ class AXI4RAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule
 }
 
 class AXI4RAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new AXI4RAMAsyncCrossing(txns)).module).io.finished
+  val dut = Module(LazyModule(new AXI4RAMAsyncCrossing(txns)).module)
+  io.finished := dut.io.finished
 }

src/main/scala/amba/axi4/Buffer.scala

@@ -53,5 +53,9 @@ object AXI4Buffer
     w:  BufferParams,
     b:  BufferParams,
     ar: BufferParams,
-    r:  BufferParams)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Buffer(aw, w, b, ar, r)).node
+    r:  BufferParams)(implicit p: Parameters): AXI4Node =
+  {
+    val axi4buf = LazyModule(new AXI4Buffer(aw, w, b, ar, r))
+    axi4buf.node
+  }
 }

src/main/scala/amba/axi4/Deinterleaver.scala

@@ -99,5 +99,9 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
 
 object AXI4Deinterleaver
 {
-  def apply(maxReadBytes: Int)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Deinterleaver(maxReadBytes)).node
+  def apply(maxReadBytes: Int)(implicit p: Parameters): AXI4Node =
+  {
+    val axi4deint = LazyModule(new AXI4Deinterleaver(maxReadBytes))
+    axi4deint.node
+  }
 }

src/main/scala/amba/axi4/Delayer.scala

@@ -79,5 +79,9 @@ class AXI4Delayer(q: Double)(implicit p: Parameters) extends LazyModule
 
 object AXI4Delayer
 {
-  def apply(q: Double)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Delayer(q)).node
+  def apply(q: Double)(implicit p: Parameters): AXI4Node =
+  {
+    val axi4delay = LazyModule(new AXI4Delayer(q))
+    axi4delay.node
+  }
 }

src/main/scala/amba/axi4/Filter.scala

@@ -58,5 +58,9 @@ object AXI4Filter
   def apply(
     Sfilter: AXI4SlaveParameters  => Option[AXI4SlaveParameters]   = AXI4Filter.Sidentity,
     Mfilter: AXI4MasterParameters => Option[AXI4MasterParameters]  = AXI4Filter.Midentity
-    )(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Filter(Sfilter, Mfilter)).node
+    )(implicit p: Parameters): AXI4Node =
+  {
+    val axi4filt = LazyModule(new AXI4Filter(Sfilter, Mfilter))
+    axi4filt.node
+  }
 }

src/main/scala/amba/axi4/Fragmenter.scala

@@ -199,5 +199,9 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
 
 object AXI4Fragmenter
 {
-  def apply()(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Fragmenter).node
+  def apply()(implicit p: Parameters): AXI4Node =
+  {
+    val axi4frag = LazyModule(new AXI4Fragmenter)
+    axi4frag.node
+  }
 }

src/main/scala/amba/axi4/IdIndexer.scala

@@ -75,5 +75,9 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
 
 object AXI4IdIndexer
 {
-  def apply(idBits: Int)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4IdIndexer(idBits)).node
+  def apply(idBits: Int)(implicit p: Parameters): AXI4Node =
+  {
+    val axi4index = LazyModule(new AXI4IdIndexer(idBits))
+    axi4index.node
+  }
 }

src/main/scala/amba/axi4/SRAM.scala

@@ -99,5 +99,9 @@ object AXI4RAM
     beatBytes: Int = 4,
     devName: Option[String] = None,
     errors: Seq[AddressSet] = Nil)
-  (implicit p: Parameters) = LazyModule(new AXI4RAM(address, executable, beatBytes, devName, errors)).node
+  (implicit p: Parameters) =
+  {
+    val axi4ram = LazyModule(new AXI4RAM(address, executable, beatBytes, devName, errors))
+    axi4ram.node
+  }
 }

src/main/scala/amba/axi4/ToTL.scala

@@ -160,5 +160,9 @@ class AXI4BundleRError(params: AXI4BundleParameters) extends AXI4BundleBase(para
 
 object AXI4ToTL
 {
-  def apply()(implicit p: Parameters) = LazyModule(new AXI4ToTL).node
+  def apply()(implicit p: Parameters) =
+  {
+    val axi42tl = LazyModule(new AXI4ToTL)
+    axi42tl.node
+  }
 }

src/main/scala/amba/axi4/UserYanker.scala

@@ -91,5 +91,9 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
 
 object AXI4UserYanker
 {
-  def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4UserYanker(capMaxFlight)).node
+  def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node =
+  {
+    val axi4yank = LazyModule(new AXI4UserYanker(capMaxFlight))
+    axi4yank.node
+  }
 }

src/main/scala/amba/axi4/Xbar.scala

@@ -205,7 +205,11 @@ object AXI4Xbar
   def apply(
     arbitrationPolicy: TLArbiter.Policy = TLArbiter.roundRobin,
     maxFlightPerId:    Int = 7,
-    awQueueDepth:      Int = 2)(implicit p: Parameters) = LazyModule(new AXI4Xbar(arbitrationPolicy, maxFlightPerId, awQueueDepth)).node
+    awQueueDepth:      Int = 2)(implicit p: Parameters) =
+  {
+    val axi4xbar = LazyModule(new AXI4Xbar(arbitrationPolicy, maxFlightPerId, awQueueDepth))
+    axi4xbar.node
+  }
 
   def mapInputIds(ports: Seq[AXI4MasterPortParameters]) = TLXbar.assignRanges(ports.map(_.endId)).map(_.get)