108 lines
3.5 KiB
Scala
108 lines
3.5 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.util.IrrevocableIO
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util.{leftOR, rightOR, UIntToOH1, OH1ToOH}
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import scala.math.{min,max}
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class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyModule
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{
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require (maxReadBytes >= 1 && isPow2(maxReadBytes))
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val node = AXI4AdapterNode(
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masterFn = { mp => mp },
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slaveFn = { sp => sp.copy(slaves = sp.slaves.map(s => s.copy(
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supportsRead = s.supportsRead.intersect(TransferSizes(1, maxReadBytes)),
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interleavedId = Some(0))))
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})
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val endId = edgeOut.master.endId
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val beatBytes = edgeOut.slave.beatBytes
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val beats = (maxReadBytes+beatBytes-1) / beatBytes
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// This adapter leaves the control + write paths completely untouched
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out.ar <> in.ar
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out.aw <> in.aw
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out.w <> in.w
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in.b <> out.b
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if (beats <= 1) {
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// Nothing to do if only single-beat R
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in.r <> out.r
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} else {
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// Queues to buffer R responses
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val qs = Seq.tabulate(endId) { i =>
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val depth = edgeOut.master.masters.find(_.id.contains(i)).flatMap(_.maxFlight).getOrElse(0)
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if (depth > 0) {
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Module(new Queue(out.r.bits.cloneType, beats)).io
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} else {
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Wire(new QueueIO(out.r.bits.cloneType, beats))
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}
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}
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// Which ID is being enqueued and dequeued?
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val locked = RegInit(Bool(false))
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val deq_id = Reg(UInt(width=log2Up(endId)))
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val enq_id = out.r.bits.id
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val deq_OH = UIntToOH(deq_id, endId)
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val enq_OH = UIntToOH(enq_id, endId)
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// Track the number of completely received bursts per FIFO id
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val pending = Cat(Seq.tabulate(endId) { i =>
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val depth = edgeOut.master.masters.find(_.id.contains(i)).flatMap(_.maxFlight).getOrElse(0)
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if (depth == 0) {
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Bool(false)
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} else {
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val count = RegInit(UInt(0, width=log2Ceil(beats+1)))
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val next = Wire(count)
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val inc = enq_OH(i) && out.r.fire() && out.r.bits.last
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val dec = deq_OH(i) && in.r.fire() && in.r.bits.last
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next := count + inc.asUInt - dec.asUInt
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count := next
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// Bounds checking
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assert (!dec || count =/= UInt(0))
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assert (!inc || count =/= UInt(beats))
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next =/= UInt(0)
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}
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}.reverse)
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// Select which Q will we start sending next cycle
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val winner = pending & ~(leftOR(pending) << 1)
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when (!locked || (in.r.fire() && in.r.bits.last)) {
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locked := pending.orR
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deq_id := OHToUInt(winner)
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}
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// Transmit the selected burst to inner
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in.r.valid := locked
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in.r.bits := Vec(qs.map(_.deq.bits))(deq_id)
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(deq_OH.toBools zip qs) foreach { case (s, q) =>
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q.deq.ready := s && in.r.fire()
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}
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// Feed response into matching Q
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out.r.ready := Vec(qs.map(_.enq.ready))(enq_id)
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(enq_OH.toBools zip qs) foreach { case (s, q) =>
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q.enq.valid := s && out.r.valid
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q.enq.bits := out.r.bits
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}
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}
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}
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}
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}
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object AXI4Deinterleaver
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{
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def apply(maxReadBytes: Int)(implicit p: Parameters): AXI4Node =
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{
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val axi4deint = LazyModule(new AXI4Deinterleaver(maxReadBytes))
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axi4deint.node
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}
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}
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