From 8781d2b2e7ea53bdce4bf09202238f2d61904a7c Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Fri, 1 Dec 2017 11:27:54 -0800
Subject: [PATCH] diplomacy: provide a val name for all LazyModule
 constructions

---
 src/main/scala/amba/ahb/ToTL.scala            |  6 ++-
 src/main/scala/amba/axi4/AsyncCrossing.scala  | 13 +++--
 src/main/scala/amba/axi4/Buffer.scala         |  6 ++-
 src/main/scala/amba/axi4/Deinterleaver.scala  |  6 ++-
 src/main/scala/amba/axi4/Delayer.scala        |  6 ++-
 src/main/scala/amba/axi4/Filter.scala         |  6 ++-
 src/main/scala/amba/axi4/Fragmenter.scala     |  6 ++-
 src/main/scala/amba/axi4/IdIndexer.scala      |  6 ++-
 src/main/scala/amba/axi4/SRAM.scala           |  6 ++-
 src/main/scala/amba/axi4/ToTL.scala           |  6 ++-
 src/main/scala/amba/axi4/UserYanker.scala     |  6 ++-
 src/main/scala/amba/axi4/Xbar.scala           |  6 ++-
 src/main/scala/coreplex/CrossingWrapper.scala | 48 +++++++++----------
 src/main/scala/devices/tilelink/TestRAM.scala |  3 +-
 src/main/scala/interrupts/Crossing.scala      | 12 ++++-
 src/main/scala/tilelink/AsyncCrossing.scala   | 15 ++++--
 src/main/scala/tilelink/AtomicAutomata.scala  |  8 +++-
 src/main/scala/tilelink/Broadcast.scala       |  5 +-
 src/main/scala/tilelink/Buffer.scala          |  6 ++-
 src/main/scala/tilelink/CacheCork.scala       |  6 ++-
 src/main/scala/tilelink/Delayer.scala         |  6 ++-
 src/main/scala/tilelink/ErrorEvaluator.scala  |  5 +-
 src/main/scala/tilelink/FIFOFixer.scala       |  6 ++-
 src/main/scala/tilelink/Filter.scala          |  6 ++-
 src/main/scala/tilelink/Fragmenter.scala      |  8 +++-
 src/main/scala/tilelink/Fuzzer.scala          |  5 +-
 src/main/scala/tilelink/HintHandler.scala     |  8 +++-
 src/main/scala/tilelink/Map.scala             |  6 ++-
 src/main/scala/tilelink/NodeNumberer.scala    |  6 ++-
 src/main/scala/tilelink/PatternPusher.scala   |  5 +-
 src/main/scala/tilelink/RAMModel.scala        |  5 +-
 .../scala/tilelink/RationalCrossing.scala     | 15 ++++--
 .../scala/tilelink/RegisterRouterTest.scala   |  6 ++-
 src/main/scala/tilelink/SRAM.scala            |  8 +++-
 src/main/scala/tilelink/SourceShrinker.scala  |  6 ++-
 src/main/scala/tilelink/ToAHB.scala           |  6 ++-
 src/main/scala/tilelink/ToAPB.scala           |  6 ++-
 src/main/scala/tilelink/ToAXI4.scala          |  5 +-
 src/main/scala/tilelink/WidthWidget.scala     |  9 +++-
 src/main/scala/tilelink/Xbar.scala            | 11 +++--
 40 files changed, 242 insertions(+), 78 deletions(-)

diff --git a/src/main/scala/amba/ahb/ToTL.scala b/src/main/scala/amba/ahb/ToTL.scala
index 4b0484ba..c3a97633 100644
--- a/src/main/scala/amba/ahb/ToTL.scala
+++ b/src/main/scala/amba/ahb/ToTL.scala
@@ -138,5 +138,9 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
 
 object AHBToTL
 {
-  def apply()(implicit p: Parameters) = LazyModule(new AHBToTL).node
+  def apply()(implicit p: Parameters) =
+  {
+    val ahb2tl = LazyModule(new AHBToTL)
+    ahb2tl.node
+  }
 }
diff --git a/src/main/scala/amba/axi4/AsyncCrossing.scala b/src/main/scala/amba/axi4/AsyncCrossing.scala
index 0eb9daf3..3110ef23 100644
--- a/src/main/scala/amba/axi4/AsyncCrossing.scala
+++ b/src/main/scala/amba/axi4/AsyncCrossing.scala
@@ -43,12 +43,18 @@ class AXI4AsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameter
 
 object AXI4AsyncCrossingSource
 {
-  def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new AXI4AsyncCrossingSource(sync)).node
+  def apply(sync: Int = 3)(implicit p: Parameters) = {
+    val axi4asource = LazyModule(new AXI4AsyncCrossingSource(sync))
+    axi4asource.node
+  }
 }
 
 object AXI4AsyncCrossingSink
 {
-  def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) = LazyModule(new AXI4AsyncCrossingSink(depth, sync)).node
+  def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) = {
+    val axi4asink = LazyModule(new AXI4AsyncCrossingSink(depth, sync))
+    axi4asink.node
+  }
 }
 
 @deprecated("AXI4AsyncCrossing is fragile. Use AXI4AsyncCrossingSource and AXI4AsyncCrossingSink", "rocket-chip 1.2")
@@ -99,5 +105,6 @@ class AXI4RAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule
 }
 
 class AXI4RAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new AXI4RAMAsyncCrossing(txns)).module).io.finished
+  val dut = Module(LazyModule(new AXI4RAMAsyncCrossing(txns)).module)
+  io.finished := dut.io.finished
 }
diff --git a/src/main/scala/amba/axi4/Buffer.scala b/src/main/scala/amba/axi4/Buffer.scala
index af51b6dd..1bd186d0 100644
--- a/src/main/scala/amba/axi4/Buffer.scala
+++ b/src/main/scala/amba/axi4/Buffer.scala
@@ -53,5 +53,9 @@ object AXI4Buffer
     w:  BufferParams,
     b:  BufferParams,
     ar: BufferParams,
-    r:  BufferParams)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Buffer(aw, w, b, ar, r)).node
+    r:  BufferParams)(implicit p: Parameters): AXI4Node =
+  {
+    val axi4buf = LazyModule(new AXI4Buffer(aw, w, b, ar, r))
+    axi4buf.node
+  }
 }
diff --git a/src/main/scala/amba/axi4/Deinterleaver.scala b/src/main/scala/amba/axi4/Deinterleaver.scala
index bdc9db39..1dc7862f 100644
--- a/src/main/scala/amba/axi4/Deinterleaver.scala
+++ b/src/main/scala/amba/axi4/Deinterleaver.scala
@@ -99,5 +99,9 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
 
 object AXI4Deinterleaver
 {
-  def apply(maxReadBytes: Int)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Deinterleaver(maxReadBytes)).node
+  def apply(maxReadBytes: Int)(implicit p: Parameters): AXI4Node =
+  {
+    val axi4deint = LazyModule(new AXI4Deinterleaver(maxReadBytes))
+    axi4deint.node
+  }
 }
diff --git a/src/main/scala/amba/axi4/Delayer.scala b/src/main/scala/amba/axi4/Delayer.scala
index 2ca6d1b2..cc7013f0 100644
--- a/src/main/scala/amba/axi4/Delayer.scala
+++ b/src/main/scala/amba/axi4/Delayer.scala
@@ -79,5 +79,9 @@ class AXI4Delayer(q: Double)(implicit p: Parameters) extends LazyModule
 
 object AXI4Delayer
 {
-  def apply(q: Double)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Delayer(q)).node
+  def apply(q: Double)(implicit p: Parameters): AXI4Node =
+  {
+    val axi4delay = LazyModule(new AXI4Delayer(q))
+    axi4delay.node
+  }
 }
diff --git a/src/main/scala/amba/axi4/Filter.scala b/src/main/scala/amba/axi4/Filter.scala
index 99a2e9ca..7eee69aa 100644
--- a/src/main/scala/amba/axi4/Filter.scala
+++ b/src/main/scala/amba/axi4/Filter.scala
@@ -58,5 +58,9 @@ object AXI4Filter
   def apply(
     Sfilter: AXI4SlaveParameters  => Option[AXI4SlaveParameters]   = AXI4Filter.Sidentity,
     Mfilter: AXI4MasterParameters => Option[AXI4MasterParameters]  = AXI4Filter.Midentity
-    )(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Filter(Sfilter, Mfilter)).node
+    )(implicit p: Parameters): AXI4Node =
+  {
+    val axi4filt = LazyModule(new AXI4Filter(Sfilter, Mfilter))
+    axi4filt.node
+  }
 }
diff --git a/src/main/scala/amba/axi4/Fragmenter.scala b/src/main/scala/amba/axi4/Fragmenter.scala
index b1897f84..cfffcd33 100644
--- a/src/main/scala/amba/axi4/Fragmenter.scala
+++ b/src/main/scala/amba/axi4/Fragmenter.scala
@@ -199,5 +199,9 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
 
 object AXI4Fragmenter
 {
-  def apply()(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Fragmenter).node
+  def apply()(implicit p: Parameters): AXI4Node =
+  {
+    val axi4frag = LazyModule(new AXI4Fragmenter)
+    axi4frag.node
+  }
 }
diff --git a/src/main/scala/amba/axi4/IdIndexer.scala b/src/main/scala/amba/axi4/IdIndexer.scala
index d83bf185..d9ef1323 100644
--- a/src/main/scala/amba/axi4/IdIndexer.scala
+++ b/src/main/scala/amba/axi4/IdIndexer.scala
@@ -75,5 +75,9 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
 
 object AXI4IdIndexer
 {
-  def apply(idBits: Int)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4IdIndexer(idBits)).node
+  def apply(idBits: Int)(implicit p: Parameters): AXI4Node =
+  {
+    val axi4index = LazyModule(new AXI4IdIndexer(idBits))
+    axi4index.node
+  }
 }
diff --git a/src/main/scala/amba/axi4/SRAM.scala b/src/main/scala/amba/axi4/SRAM.scala
index 26e5a318..bf9108bb 100644
--- a/src/main/scala/amba/axi4/SRAM.scala
+++ b/src/main/scala/amba/axi4/SRAM.scala
@@ -99,5 +99,9 @@ object AXI4RAM
     beatBytes: Int = 4,
     devName: Option[String] = None,
     errors: Seq[AddressSet] = Nil)
-  (implicit p: Parameters) = LazyModule(new AXI4RAM(address, executable, beatBytes, devName, errors)).node
+  (implicit p: Parameters) =
+  {
+    val axi4ram = LazyModule(new AXI4RAM(address, executable, beatBytes, devName, errors))
+    axi4ram.node
+  }
 }
diff --git a/src/main/scala/amba/axi4/ToTL.scala b/src/main/scala/amba/axi4/ToTL.scala
index 207a0353..4e27e4bf 100644
--- a/src/main/scala/amba/axi4/ToTL.scala
+++ b/src/main/scala/amba/axi4/ToTL.scala
@@ -160,5 +160,9 @@ class AXI4BundleRError(params: AXI4BundleParameters) extends AXI4BundleBase(para
 
 object AXI4ToTL
 {
-  def apply()(implicit p: Parameters) = LazyModule(new AXI4ToTL).node
+  def apply()(implicit p: Parameters) =
+  {
+    val axi42tl = LazyModule(new AXI4ToTL)
+    axi42tl.node
+  }
 }
diff --git a/src/main/scala/amba/axi4/UserYanker.scala b/src/main/scala/amba/axi4/UserYanker.scala
index f4c91808..c8bdf40f 100644
--- a/src/main/scala/amba/axi4/UserYanker.scala
+++ b/src/main/scala/amba/axi4/UserYanker.scala
@@ -91,5 +91,9 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
 
 object AXI4UserYanker
 {
-  def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4UserYanker(capMaxFlight)).node
+  def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node =
+  {
+    val axi4yank = LazyModule(new AXI4UserYanker(capMaxFlight))
+    axi4yank.node
+  }
 }
diff --git a/src/main/scala/amba/axi4/Xbar.scala b/src/main/scala/amba/axi4/Xbar.scala
index 70a8f1e7..ad5c0349 100644
--- a/src/main/scala/amba/axi4/Xbar.scala
+++ b/src/main/scala/amba/axi4/Xbar.scala
@@ -205,7 +205,11 @@ object AXI4Xbar
   def apply(
     arbitrationPolicy: TLArbiter.Policy = TLArbiter.roundRobin,
     maxFlightPerId:    Int = 7,
-    awQueueDepth:      Int = 2)(implicit p: Parameters) = LazyModule(new AXI4Xbar(arbitrationPolicy, maxFlightPerId, awQueueDepth)).node
+    awQueueDepth:      Int = 2)(implicit p: Parameters) =
+  {
+    val axi4xbar = LazyModule(new AXI4Xbar(arbitrationPolicy, maxFlightPerId, awQueueDepth))
+    axi4xbar.node
+  }
 
   def mapInputIds(ports: Seq[AXI4MasterPortParameters]) = TLXbar.assignRanges(ports.map(_.endId)).map(_.get)
 
diff --git a/src/main/scala/coreplex/CrossingWrapper.scala b/src/main/scala/coreplex/CrossingWrapper.scala
index ec638ebb..b8955b75 100644
--- a/src/main/scala/coreplex/CrossingWrapper.scala
+++ b/src/main/scala/coreplex/CrossingWrapper.scala
@@ -51,20 +51,20 @@ trait HasCrossingMethods extends LazyModule with LazyScope
   }
 
   def crossTLAsyncInOut(out: Boolean)(depth: Int = 8, sync: Int = 3)(implicit p: Parameters): TLNode = {
-    def sourceGen = LazyModule(new TLAsyncCrossingSource(sync))
-    def sinkGen = LazyModule(new TLAsyncCrossingSink(depth, sync))
-    val source = if (out) this { sourceGen } else sourceGen
-    val sink = if (out) sinkGen else this { sinkGen }
+    lazy val asource = LazyModule(new TLAsyncCrossingSource(sync))
+    lazy val asink = LazyModule(new TLAsyncCrossingSink(depth, sync))
+    val source = if (out) this { asource } else asource
+    val sink = if (out) asink else this { asink }
     sink.node :=? source.node
     checks = CrossingCheck(out, source.node, sink.node) :: checks
     NodeHandle(source.node, sink.node)
   }
 
   def crossTLRationalInOut(out: Boolean)(direction: RationalDirection)(implicit p: Parameters): TLNode = {
-    def sourceGen = LazyModule(new TLRationalCrossingSource)
-    def sinkGen = LazyModule(new TLRationalCrossingSink(if (out) direction else direction.flip))
-    val source = if (out) this { sourceGen } else sourceGen
-    val sink = if (out) sinkGen else this { sinkGen }
+    lazy val rsource = LazyModule(new TLRationalCrossingSource)
+    lazy val rsink = LazyModule(new TLRationalCrossingSink(if (out) direction else direction.flip))
+    val source = if (out) this { rsource } else rsource
+    val sink = if (out) rsink else this { rsink }
     sink.node :=? source.node
     checks = CrossingCheck(out, source.node, sink.node) :: checks
     NodeHandle(source.node, sink.node)
@@ -98,10 +98,10 @@ trait HasCrossingMethods extends LazyModule with LazyScope
   }
 
   def crossAXI4AsyncInOut(out: Boolean)(depth: Int = 8, sync: Int = 3)(implicit p: Parameters): AXI4Node = {
-    def sourceGen = LazyModule(new AXI4AsyncCrossingSource(sync))
-    def sinkGen = LazyModule(new AXI4AsyncCrossingSink(depth, sync))
-    val source = if (out) this { sourceGen } else sourceGen
-    val sink = if (out) sinkGen else this { sinkGen }
+    lazy val axi4asource = LazyModule(new AXI4AsyncCrossingSource(sync))
+    lazy val axi4asink = LazyModule(new AXI4AsyncCrossingSink(depth, sync))
+    val source = if (out) this { axi4asource } else axi4asource
+    val sink = if (out) axi4asink else this { axi4asink }
     sink.node :=? source.node
     checks = CrossingCheck(out, source.node, sink.node) :: checks
     NodeHandle(source.node, sink.node)
@@ -127,30 +127,30 @@ trait HasCrossingMethods extends LazyModule with LazyScope
   // Interrupts
 
   def crossIntSyncInOut(out: Boolean)(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
-    def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
-    def sinkGen = LazyModule(new IntSyncCrossingSink(0))
-    val source = if (out) this { sourceGen } else sourceGen
-    val sink = if (out) sinkGen else this { sinkGen }
+    lazy val intssource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
+    lazy val intssink = LazyModule(new IntSyncCrossingSink(0))
+    val source = if (out) this { intssource } else intssource
+    val sink = if (out) intssink else this { intssink }
     sink.node :=? source.node
     checks = CrossingCheck(out, source.node, sink.node) :: checks
     NodeHandle(source.node, sink.node)
   }
 
   def crossIntAsyncInOut(out: Boolean)(sync: Int = 3, alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
-    def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
-    def sinkGen = LazyModule(new IntSyncCrossingSink(sync))
-    val source = if (out) this { sourceGen } else sourceGen
-    val sink = if (out) sinkGen else this { sinkGen }
+    lazy val intasource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
+    lazy val intasink = LazyModule(new IntSyncCrossingSink(sync))
+    val source = if (out) this { intasource } else intasource
+    val sink = if (out) intasink else this { intasink }
     sink.node :=? source.node
     checks = CrossingCheck(out, source.node, sink.node) :: checks
     NodeHandle(source.node, sink.node)
   }
 
   def crossIntRationalInOut(out: Boolean)(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
-    def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
-    def sinkGen = LazyModule(new IntSyncCrossingSink(1))
-    val source = if (out) this { sourceGen } else sourceGen
-    val sink = if (out) sinkGen else this { sinkGen }
+    lazy val intrsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
+    lazy val intrsink = LazyModule(new IntSyncCrossingSink(1))
+    val source = if (out) this { intrsource } else intrsource
+    val sink = if (out) intrsink else this { intrsink }
     sink.node :=? source.node
     checks = CrossingCheck(out, source.node, sink.node) :: checks
     NodeHandle(source.node, sink.node)
diff --git a/src/main/scala/devices/tilelink/TestRAM.scala b/src/main/scala/devices/tilelink/TestRAM.scala
index 0bd6eb6d..f73d702c 100644
--- a/src/main/scala/devices/tilelink/TestRAM.scala
+++ b/src/main/scala/devices/tilelink/TestRAM.scala
@@ -75,5 +75,6 @@ class TLRAMZeroDelay(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) exten
 }
 
 class TLRAMZeroDelayTest(ramBeatBytes: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMZeroDelay(ramBeatBytes, txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMZeroDelay(ramBeatBytes, txns)).module)
+  io.finished := dut.io.finished
 }
diff --git a/src/main/scala/interrupts/Crossing.scala b/src/main/scala/interrupts/Crossing.scala
index 628dc53a..68054551 100644
--- a/src/main/scala/interrupts/Crossing.scala
+++ b/src/main/scala/interrupts/Crossing.scala
@@ -21,7 +21,11 @@ class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
 
 object IntSyncCrossingSource
 {
-  def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = LazyModule(new IntSyncCrossingSource(alreadyRegistered)).node
+  def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
+  {
+    val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
+    intsource.node
+  }
 }
 
 
@@ -54,5 +58,9 @@ class IntSyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyMod
 
 object IntSyncCrossingSink
 {
-  def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new IntSyncCrossingSink(sync)).node
+  def apply(sync: Int = 3)(implicit p: Parameters) =
+  {
+    val intsink = LazyModule(new IntSyncCrossingSink(sync))
+    intsink.node
+  }
 }
diff --git a/src/main/scala/tilelink/AsyncCrossing.scala b/src/main/scala/tilelink/AsyncCrossing.scala
index eb44cc15..4e4a9300 100644
--- a/src/main/scala/tilelink/AsyncCrossing.scala
+++ b/src/main/scala/tilelink/AsyncCrossing.scala
@@ -78,12 +78,20 @@ class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameters)
 
 object TLAsyncCrossingSource
 {
-  def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new TLAsyncCrossingSource(sync)).node
+  def apply(sync: Int = 3)(implicit p: Parameters) =
+  {
+    val asource = LazyModule(new TLAsyncCrossingSource(sync))
+    asource.node
+  }
 }
 
 object TLAsyncCrossingSink
 {
-  def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) = LazyModule(new TLAsyncCrossingSink(depth, sync)).node
+  def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) =
+  {
+    val asink = LazyModule(new TLAsyncCrossingSink(depth, sync))
+    asink.node
+  }
 }
 
 @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2")
@@ -131,5 +139,6 @@ class TLRAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
 }
 
 class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMAsyncCrossing(txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module)
+  io.finished := dut.io.finished
 }
diff --git a/src/main/scala/tilelink/AtomicAutomata.scala b/src/main/scala/tilelink/AtomicAutomata.scala
index 2e8a1a5b..53222472 100644
--- a/src/main/scala/tilelink/AtomicAutomata.scala
+++ b/src/main/scala/tilelink/AtomicAutomata.scala
@@ -266,7 +266,10 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
 object TLAtomicAutomata
 {
   def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters): TLNode =
-    LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough)).node
+  {
+    val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough))
+    atomics.node
+  }
 
   case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int)
 
@@ -318,5 +321,6 @@ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule
 }
 
 class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMAtomicAutomata(txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module)
+  io.finished := dut.io.finished
 }
diff --git a/src/main/scala/tilelink/Broadcast.scala b/src/main/scala/tilelink/Broadcast.scala
index ea76657c..1e289530 100644
--- a/src/main/scala/tilelink/Broadcast.scala
+++ b/src/main/scala/tilelink/Broadcast.scala
@@ -208,7 +208,10 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
 object TLBroadcast
 {
   def apply(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = false)(implicit p: Parameters): TLNode =
-    LazyModule(new TLBroadcast(lineBytes, numTrackers, bufferless)).node
+  {
+    val broadcast = LazyModule(new TLBroadcast(lineBytes, numTrackers, bufferless))
+    broadcast.node
+  }
 }
 
 class TLBroadcastTracker(id: Int, lineBytes: Int, probeCountBits: Int, bufferless: Boolean, edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Module
diff --git a/src/main/scala/tilelink/Buffer.scala b/src/main/scala/tilelink/Buffer.scala
index 51310494..4305d1a5 100644
--- a/src/main/scala/tilelink/Buffer.scala
+++ b/src/main/scala/tilelink/Buffer.scala
@@ -64,7 +64,11 @@ object TLBuffer
       b: BufferParams,
       c: BufferParams,
       d: BufferParams,
-      e: BufferParams)(implicit p: Parameters): TLNode = LazyModule(new TLBuffer(a, b, c, d, e)).node
+      e: BufferParams)(implicit p: Parameters): TLNode =
+  {
+    val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
+    buffer.node
+  }
 
   def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
     val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
diff --git a/src/main/scala/tilelink/CacheCork.scala b/src/main/scala/tilelink/CacheCork.scala
index c614f02d..7a52f7c0 100644
--- a/src/main/scala/tilelink/CacheCork.scala
+++ b/src/main/scala/tilelink/CacheCork.scala
@@ -121,5 +121,9 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM
 
 object TLCacheCork
 {
-  def apply(unsafe: Boolean = false)(implicit p: Parameters): TLNode = LazyModule(new TLCacheCork(unsafe)).node
+  def apply(unsafe: Boolean = false)(implicit p: Parameters): TLNode =
+  {
+    val cork = LazyModule(new TLCacheCork(unsafe))
+    cork.node
+  }
 }
diff --git a/src/main/scala/tilelink/Delayer.scala b/src/main/scala/tilelink/Delayer.scala
index 11f75c05..965e3633 100644
--- a/src/main/scala/tilelink/Delayer.scala
+++ b/src/main/scala/tilelink/Delayer.scala
@@ -72,5 +72,9 @@ class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule
 
 object TLDelayer
 {
-  def apply(q: Double)(implicit p: Parameters): TLNode = LazyModule(new TLDelayer(q)).node
+  def apply(q: Double)(implicit p: Parameters): TLNode =
+  {
+    val delayer = LazyModule(new TLDelayer(q))
+    delayer.node
+  }
 }
diff --git a/src/main/scala/tilelink/ErrorEvaluator.scala b/src/main/scala/tilelink/ErrorEvaluator.scala
index 1bcd71a0..37067d0b 100644
--- a/src/main/scala/tilelink/ErrorEvaluator.scala
+++ b/src/main/scala/tilelink/ErrorEvaluator.scala
@@ -62,5 +62,8 @@ class TLErrorEvaluator(test: RequestPattern, testOn: Boolean, testOff: Boolean)(
 object TLErrorEvaluator
 {
   def apply(test: RequestPattern, testOn: Boolean = false, testOff: Boolean = false)(implicit p: Parameters): TLNode =
-    LazyModule(new TLErrorEvaluator(test, testOn, testOff)).node
+  {
+    val errors = LazyModule(new TLErrorEvaluator(test, testOn, testOff))
+    errors.node
+  }
 }
diff --git a/src/main/scala/tilelink/FIFOFixer.scala b/src/main/scala/tilelink/FIFOFixer.scala
index 38634a4f..bd3adab2 100644
--- a/src/main/scala/tilelink/FIFOFixer.scala
+++ b/src/main/scala/tilelink/FIFOFixer.scala
@@ -113,5 +113,9 @@ object TLFIFOFixer
   val allFIFO:        Policy = m => m.fifoId.isDefined
   val allUncacheable: Policy = m => m.regionType <= UNCACHEABLE
 
-  def apply(policy: Policy = all)(implicit p: Parameters): TLNode = LazyModule(new TLFIFOFixer(policy)).node
+  def apply(policy: Policy = all)(implicit p: Parameters): TLNode =
+  {
+    val fixer = LazyModule(new TLFIFOFixer(policy))
+    fixer.node
+  }
 }
diff --git a/src/main/scala/tilelink/Filter.scala b/src/main/scala/tilelink/Filter.scala
index 9465727a..be68b91c 100644
--- a/src/main/scala/tilelink/Filter.scala
+++ b/src/main/scala/tilelink/Filter.scala
@@ -91,5 +91,9 @@ object TLFilter
   def apply(
     Mfilter: TLManagerParameters => Option[TLManagerParameters] = TLFilter.Midentity,
     Cfilter: TLClientParameters  => Option[TLClientParameters]  = TLFilter.Cidentity
-    )(implicit p: Parameters): TLNode = LazyModule(new TLFilter(Mfilter, Cfilter)).node
+    )(implicit p: Parameters): TLNode =
+  {
+    val filter = LazyModule(new TLFilter(Mfilter, Cfilter))
+    filter.node
+  }
 }
diff --git a/src/main/scala/tilelink/Fragmenter.scala b/src/main/scala/tilelink/Fragmenter.scala
index dad9bfc8..ae82a72e 100644
--- a/src/main/scala/tilelink/Fragmenter.scala
+++ b/src/main/scala/tilelink/Fragmenter.scala
@@ -294,7 +294,10 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
 object TLFragmenter
 {
   def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None)(implicit p: Parameters): TLNode =
-    LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck)).node
+  {
+    val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck))
+    fragmenter.node
+  }
 }
 
 /** Synthesizeable unit tests */
@@ -324,5 +327,6 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Pa
 }
 
 class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module)
+  io.finished := dut.io.finished
 }
diff --git a/src/main/scala/tilelink/Fuzzer.scala b/src/main/scala/tilelink/Fuzzer.scala
index e43e4915..8c6fdc0b 100644
--- a/src/main/scala/tilelink/Fuzzer.scala
+++ b/src/main/scala/tilelink/Fuzzer.scala
@@ -233,7 +233,10 @@ object TLFuzzer
     noModify: Boolean = false,
     overrideAddress: Option[AddressSet] = None,
     nOrdered: Option[Int] = None)(implicit p: Parameters): TLOutwardNode =
-    LazyModule(new TLFuzzer(nOperations, inFlight, noiseMaker, noModify, overrideAddress, nOrdered)).node
+  {
+    val fuzzer = LazyModule(new TLFuzzer(nOperations, inFlight, noiseMaker, noModify, overrideAddress, nOrdered))
+    fuzzer.node
+  }
 }
 
 /** Synthesizeable integration test */
diff --git a/src/main/scala/tilelink/HintHandler.scala b/src/main/scala/tilelink/HintHandler.scala
index 78003bbd..ba0ae383 100644
--- a/src/main/scala/tilelink/HintHandler.scala
+++ b/src/main/scala/tilelink/HintHandler.scala
@@ -92,7 +92,10 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
 object TLHintHandler
 {
   def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit p: Parameters): TLNode =
-    LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough)).node
+  {
+    val hints = LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough))
+    hints.node
+  }
 }
 
 /** Synthesizeable unit tests */
@@ -119,5 +122,6 @@ class TLRAMHintHandler(txns: Int)(implicit p: Parameters) extends LazyModule {
 }
 
 class TLRAMHintHandlerTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMHintHandler(txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMHintHandler(txns)).module)
+  io.finished := dut.io.finished
 }
diff --git a/src/main/scala/tilelink/Map.scala b/src/main/scala/tilelink/Map.scala
index c0ceaabb..f63d0836 100644
--- a/src/main/scala/tilelink/Map.scala
+++ b/src/main/scala/tilelink/Map.scala
@@ -38,5 +38,9 @@ class TLMap(fn: AddressSet => BigInt)(implicit p: Parameters) extends LazyModule
 
 object TLMap
 {
-  def apply(fn: AddressSet => BigInt)(implicit p: Parameters): TLNode = LazyModule(new TLMap(fn)).node
+  def apply(fn: AddressSet => BigInt)(implicit p: Parameters): TLNode =
+  {
+    val map = LazyModule(new TLMap(fn))
+    map.node
+  }
 }
diff --git a/src/main/scala/tilelink/NodeNumberer.scala b/src/main/scala/tilelink/NodeNumberer.scala
index 6394a1f4..57601b67 100644
--- a/src/main/scala/tilelink/NodeNumberer.scala
+++ b/src/main/scala/tilelink/NodeNumberer.scala
@@ -55,5 +55,9 @@ class TLNodeNumberer(nodeAddressOffset: Option[Int] = None)(implicit p: Paramete
 
 object TLNodeNumberer
 {
-  def apply(nodeAddressOffset: Option[Int] = None)(implicit p: Parameters): TLNode = LazyModule(new TLNodeNumberer(nodeAddressOffset)).node
+  def apply(nodeAddressOffset: Option[Int] = None)(implicit p: Parameters): TLNode =
+  {
+    val numberer = LazyModule(new TLNodeNumberer(nodeAddressOffset))
+    numberer.node
+  }
 }
diff --git a/src/main/scala/tilelink/PatternPusher.scala b/src/main/scala/tilelink/PatternPusher.scala
index f249946d..60ab48cc 100644
--- a/src/main/scala/tilelink/PatternPusher.scala
+++ b/src/main/scala/tilelink/PatternPusher.scala
@@ -88,5 +88,8 @@ class TLPatternPusher(name: String, pattern: Seq[Pattern])(implicit p: Parameter
 object TLPatternPusher
 {
   def apply(name: String, pattern: Seq[Pattern])(implicit p: Parameters): TLOutwardNode =
-    LazyModule(new TLPatternPusher(name, pattern)).node
+  {
+    val pusher = LazyModule(new TLPatternPusher(name, pattern))
+    pusher.node
+  }
 }
diff --git a/src/main/scala/tilelink/RAMModel.scala b/src/main/scala/tilelink/RAMModel.scala
index a8dceb4f..69900731 100644
--- a/src/main/scala/tilelink/RAMModel.scala
+++ b/src/main/scala/tilelink/RAMModel.scala
@@ -334,7 +334,10 @@ class TLRAMModel(log: String = "", ignoreErrorData: Boolean = false)(implicit p:
 object TLRAMModel
 {
   def apply(log: String = "", ignoreErrorData: Boolean = false)(implicit p: Parameters): TLNode =
-    LazyModule(new TLRAMModel(log, ignoreErrorData)).node
+  {
+    val model = LazyModule(new TLRAMModel(log, ignoreErrorData))
+    model.node
+  }
 
   case class MonitorParameters(addressBits: Int, sizeBits: Int)
 
diff --git a/src/main/scala/tilelink/RationalCrossing.scala b/src/main/scala/tilelink/RationalCrossing.scala
index 9d935b68..0136b88d 100644
--- a/src/main/scala/tilelink/RationalCrossing.scala
+++ b/src/main/scala/tilelink/RationalCrossing.scala
@@ -78,12 +78,20 @@ class TLRationalCrossingSink(direction: RationalDirection = Symmetric)(implicit
 
 object TLRationalCrossingSource
 {
-  def apply()(implicit p: Parameters) = LazyModule(new TLRationalCrossingSource).node
+  def apply()(implicit p: Parameters) =
+  {
+    val rsource = LazyModule(new TLRationalCrossingSource)
+    rsource.node
+  }
 }
 
 object TLRationalCrossingSink
 {
-  def apply(direction: RationalDirection = Symmetric)(implicit p: Parameters) = LazyModule(new TLRationalCrossingSink(direction)).node
+  def apply(direction: RationalDirection = Symmetric)(implicit p: Parameters) =
+  {
+    val rsink = LazyModule(new TLRationalCrossingSink(direction))
+    rsink.node
+  }
 }
 
 @deprecated("TLRationalCrossing is fragile. Use TLRationalCrossingSource and TLRationalCrossingSink", "rocket-chip 1.2")
@@ -189,5 +197,6 @@ class TLRAMRationalCrossing(txns: Int)(implicit p: Parameters) extends LazyModul
 }
 
 class TLRAMRationalCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMRationalCrossing(txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMRationalCrossing(txns)).module)
+  io.finished := dut.io.finished
 }
diff --git a/src/main/scala/tilelink/RegisterRouterTest.scala b/src/main/scala/tilelink/RegisterRouterTest.scala
index d7157c83..126e0ea6 100644
--- a/src/main/scala/tilelink/RegisterRouterTest.scala
+++ b/src/main/scala/tilelink/RegisterRouterTest.scala
@@ -268,7 +268,8 @@ class FuzzRRTest0(txns: Int)(implicit p: Parameters) extends LazyModule {
 }
 
 class TLRR0Test(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new FuzzRRTest0(txns)).module).io.finished
+  val dut = Module(LazyModule(new FuzzRRTest0(txns)).module)
+  io.finished := dut.io.finished
 }
 
 class FuzzRRTest1(txns: Int)(implicit p: Parameters) extends LazyModule {
@@ -283,6 +284,7 @@ class FuzzRRTest1(txns: Int)(implicit p: Parameters) extends LazyModule {
 }
 
 class TLRR1Test(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new FuzzRRTest1(txns)).module).io.finished
+  val dut = Module(LazyModule(new FuzzRRTest1(txns)).module)
+  io.finished := dut.io.finished
 }
 
diff --git a/src/main/scala/tilelink/SRAM.scala b/src/main/scala/tilelink/SRAM.scala
index c00691ba..cc664db6 100644
--- a/src/main/scala/tilelink/SRAM.scala
+++ b/src/main/scala/tilelink/SRAM.scala
@@ -90,7 +90,10 @@ object TLRAM
     beatBytes: Int = 4,
     devName: Option[String] = None,
     errors: Seq[AddressSet] = Nil)(implicit p: Parameters): TLInwardNode =
-    LazyModule(new TLRAM(address, cacheable, executable, beatBytes, devName, errors)).node
+  {
+    val ram = LazyModule(new TLRAM(address, cacheable, executable, beatBytes, devName, errors))
+    ram.node
+  }
 }
 
 /** Synthesizeable unit testing */
@@ -109,5 +112,6 @@ class TLRAMSimple(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) extends
 }
 
 class TLRAMSimpleTest(ramBeatBytes: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMSimple(ramBeatBytes, txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMSimple(ramBeatBytes, txns)).module)
+  io.finished := dut.io.finished
 }
diff --git a/src/main/scala/tilelink/SourceShrinker.scala b/src/main/scala/tilelink/SourceShrinker.scala
index 255b4a37..380c8eaa 100644
--- a/src/main/scala/tilelink/SourceShrinker.scala
+++ b/src/main/scala/tilelink/SourceShrinker.scala
@@ -74,5 +74,9 @@ class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyMod
 
 object TLSourceShrinker
 {
-  def apply(maxInFlight: Int)(implicit p: Parameters): TLNode = LazyModule(new TLSourceShrinker(maxInFlight)).node
+  def apply(maxInFlight: Int)(implicit p: Parameters): TLNode =
+  {
+    val shrinker = LazyModule(new TLSourceShrinker(maxInFlight))
+    shrinker.node
+  }
 }
diff --git a/src/main/scala/tilelink/ToAHB.scala b/src/main/scala/tilelink/ToAHB.scala
index 77b129d0..d95ba88e 100644
--- a/src/main/scala/tilelink/ToAHB.scala
+++ b/src/main/scala/tilelink/ToAHB.scala
@@ -186,5 +186,9 @@ class TLToAHB(val aFlow: Boolean = false)(implicit p: Parameters) extends LazyMo
 
 object TLToAHB
 {
-  def apply(aFlow: Boolean = true)(implicit p: Parameters) = LazyModule(new TLToAHB(aFlow)).node
+  def apply(aFlow: Boolean = true)(implicit p: Parameters) =
+  {
+    val tl2ahb = LazyModule(new TLToAHB(aFlow))
+    tl2ahb.node
+  }
 }
diff --git a/src/main/scala/tilelink/ToAPB.scala b/src/main/scala/tilelink/ToAPB.scala
index b0146090..22b6ec21 100644
--- a/src/main/scala/tilelink/ToAPB.scala
+++ b/src/main/scala/tilelink/ToAPB.scala
@@ -85,5 +85,9 @@ class TLToAPB(val aFlow: Boolean = true)(implicit p: Parameters) extends LazyMod
 
 object TLToAPB
 {
-  def apply(aFlow: Boolean = true)(implicit p: Parameters) = LazyModule(new TLToAPB(aFlow)).node
+  def apply(aFlow: Boolean = true)(implicit p: Parameters) =
+  {
+    val tl2apb = LazyModule(new TLToAPB(aFlow))
+    tl2apb.node
+  }
 }
diff --git a/src/main/scala/tilelink/ToAXI4.scala b/src/main/scala/tilelink/ToAXI4.scala
index ee3c07f3..2b733766 100644
--- a/src/main/scala/tilelink/ToAXI4.scala
+++ b/src/main/scala/tilelink/ToAXI4.scala
@@ -227,7 +227,10 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String
 object TLToAXI4
 {
   def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0)(implicit p: Parameters) =
-    LazyModule(new TLToAXI4(combinational, adapterName, stripBits)).node
+  {
+    val tl2axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits))
+    tl2axi4.node
+  }
 
   def sortByType(a: TLClientParameters, b: TLClientParameters): Boolean = {
     if ( a.supportsProbe && !b.supportsProbe) return false
diff --git a/src/main/scala/tilelink/WidthWidget.scala b/src/main/scala/tilelink/WidthWidget.scala
index 1f3b9dd1..fa74cf1b 100644
--- a/src/main/scala/tilelink/WidthWidget.scala
+++ b/src/main/scala/tilelink/WidthWidget.scala
@@ -184,7 +184,11 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod
 
 object TLWidthWidget
 {
-  def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = LazyModule(new TLWidthWidget(innerBeatBytes)).node
+  def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
+  {
+    val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
+    widget.node
+  }
 }
 
 /** Synthesizeable unit tests */
@@ -210,5 +214,6 @@ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameter
 }
 
 class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
+  io.finished := dut.io.finished
 }
diff --git a/src/main/scala/tilelink/Xbar.scala b/src/main/scala/tilelink/Xbar.scala
index b9c39ac1..52bb6d9e 100644
--- a/src/main/scala/tilelink/Xbar.scala
+++ b/src/main/scala/tilelink/Xbar.scala
@@ -205,7 +205,10 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
 object TLXbar
 {
   def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters): TLNode =
-    LazyModule(new TLXbar(policy)).node
+  {
+    val xbar = LazyModule(new TLXbar(policy))
+    xbar.node
+  }
 
   def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId)).map(_.get)
   def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))
@@ -267,7 +270,8 @@ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyM
 }
 
 class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMXbar(nManagers,txns)).module).io.finished
+  val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
+  io.finished := dut.io.finished
 }
 
 class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
@@ -290,5 +294,6 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Pa
 }
 
 class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module).io.finished
+  val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
+  io.finished := dut.io.finished
 }