62 lines
2.0 KiB
Scala
62 lines
2.0 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.util.IrrevocableIO
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import scala.math.{min,max}
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// pipe is only used if a queue has depth = 1
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class AXI4Buffer(
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aw: BufferParams,
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w: BufferParams,
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b: BufferParams,
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ar: BufferParams,
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r: BufferParams)(implicit p: Parameters) extends LazyModule
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{
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def this(aw: BufferParams, br: BufferParams)(implicit p: Parameters) = this(aw, aw, br, aw, br)
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def this(x: BufferParams)(implicit p: Parameters) = this(x, x)
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def this()(implicit p: Parameters) = this(BufferParams.default)
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val node = AXI4AdapterNode(
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masterFn = { p => p },
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slaveFn = { p => p.copy(minLatency = p.minLatency + min(aw.latency,ar.latency) + min(r.latency,b.latency)) })
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lazy val module = new LazyModuleImp(this) {
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def buffer[T <: Data](config: BufferParams, data: IrrevocableIO[T]): IrrevocableIO[T] = {
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if (config.isDefined) {
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Queue.irrevocable(data, config.depth, pipe=config.pipe, flow=config.flow)
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} else {
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data
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}
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}
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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out.aw <> buffer(aw, in .aw)
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out.w <> buffer(w, in .w)
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in .b <> buffer(b, out.b)
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out.ar <> buffer(ar, in .ar)
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in .r <> buffer(r, out.r)
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}
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}
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}
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object AXI4Buffer
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{
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def apply() (implicit p: Parameters): AXI4Node = apply(BufferParams.default)
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def apply(z: BufferParams) (implicit p: Parameters): AXI4Node = apply(z, z)
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def apply(aw: BufferParams, br: BufferParams)(implicit p: Parameters): AXI4Node = apply(aw, aw, br, aw, br)
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def apply(
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aw: BufferParams,
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w: BufferParams,
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b: BufferParams,
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ar: BufferParams,
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r: BufferParams)(implicit p: Parameters): AXI4Node =
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{
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val axi4buf = LazyModule(new AXI4Buffer(aw, w, b, ar, r))
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axi4buf.node
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}
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}
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