108 lines
3.3 KiB
Scala
108 lines
3.3 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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class AXI4RAM(
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address: AddressSet,
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executable: Boolean = true,
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beatBytes: Int = 4,
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devName: Option[String] = None,
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errors: Seq[AddressSet] = Nil)
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(implicit p: Parameters) extends DiplomaticSRAM(address, beatBytes, devName)
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{
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val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
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Seq(AXI4SlaveParameters(
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address = List(address) ++ errors,
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resources = resources,
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regionType = RegionType.UNCACHED,
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executable = executable,
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supportsRead = TransferSizes(1, beatBytes),
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supportsWrite = TransferSizes(1, beatBytes),
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interleavedId = Some(0))),
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beatBytes = beatBytes,
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minLatency = 1)))
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lazy val module = new LazyModuleImp(this) {
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val (in, _) = node.in(0)
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val mem = makeSinglePortedByteWriteSeqMem(1 << mask.filter(b=>b).size)
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val r_addr = Cat((mask zip (in.ar.bits.addr >> log2Ceil(beatBytes)).toBools).filter(_._1).map(_._2).reverse)
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val w_addr = Cat((mask zip (in.aw.bits.addr >> log2Ceil(beatBytes)).toBools).filter(_._1).map(_._2).reverse)
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val r_sel0 = address.contains(in.ar.bits.addr)
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val w_sel0 = address.contains(in.aw.bits.addr)
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val w_full = RegInit(Bool(false))
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val w_id = Reg(UInt())
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val w_user = Reg(UInt(width = 1 max in.params.userBits))
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val r_sel1 = Reg(r_sel0)
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val w_sel1 = Reg(w_sel0)
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when (in. b.fire()) { w_full := Bool(false) }
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when (in.aw.fire()) { w_full := Bool(true) }
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when (in.aw.fire()) {
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w_id := in.aw.bits.id
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w_sel1 := w_sel0
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in.aw.bits.user.foreach { w_user := _ }
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}
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val wdata = Vec.tabulate(beatBytes) { i => in.w.bits.data(8*(i+1)-1, 8*i) }
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when (in.aw.fire() && w_sel0) {
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mem.write(w_addr, wdata, in.w.bits.strb.toBools)
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}
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in. b.valid := w_full
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in.aw.ready := in. w.valid && (in.b.ready || !w_full)
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in. w.ready := in.aw.valid && (in.b.ready || !w_full)
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in.b.bits.id := w_id
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in.b.bits.resp := Mux(w_sel1, AXI4Parameters.RESP_OKAY, AXI4Parameters.RESP_DECERR)
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in.b.bits.user.foreach { _ := w_user }
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val r_full = RegInit(Bool(false))
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val r_id = Reg(UInt())
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val r_user = Reg(UInt(width = 1 max in.params.userBits))
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when (in. r.fire()) { r_full := Bool(false) }
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when (in.ar.fire()) { r_full := Bool(true) }
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when (in.ar.fire()) {
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r_id := in.ar.bits.id
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r_sel1 := r_sel0
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in.ar.bits.user.foreach { r_user := _ }
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}
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val ren = in.ar.fire()
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val rdata = mem.readAndHold(r_addr, ren)
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in. r.valid := r_full
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in.ar.ready := in.r.ready || !r_full
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in.r.bits.id := r_id
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in.r.bits.resp := Mux(r_sel1, AXI4Parameters.RESP_OKAY, AXI4Parameters.RESP_DECERR)
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in.r.bits.data := Cat(rdata.reverse)
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in.r.bits.user.foreach { _ := r_user }
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in.r.bits.last := Bool(true)
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}
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}
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object AXI4RAM
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{
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def apply(
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address: AddressSet,
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executable: Boolean = true,
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beatBytes: Int = 4,
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devName: Option[String] = None,
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errors: Seq[AddressSet] = Nil)
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(implicit p: Parameters) =
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{
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val axi4ram = LazyModule(new AXI4RAM(address, executable, beatBytes, devName, errors))
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axi4ram.node
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}
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}
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