208 lines
9.0 KiB
Scala
208 lines
9.0 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.util.IrrevocableIO
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util.{leftOR, rightOR, UIntToOH1, OH1ToOH}
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import scala.math.{min,max}
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class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
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{
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val maxBeats = 1 << AXI4Parameters.lenBits
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def expandTransfer(x: TransferSizes, beatBytes: Int, alignment: BigInt) =
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if (!x) x else TransferSizes(x.min, alignment.min(maxBeats*beatBytes).intValue)
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def mapSlave(s: AXI4SlaveParameters, beatBytes: Int) = s.copy(
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supportsWrite = expandTransfer(s.supportsWrite, beatBytes, s.minAlignment),
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supportsRead = expandTransfer(s.supportsRead, beatBytes, s.minAlignment),
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interleavedId = None) // this breaks interleaving guarantees
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def mapMaster(m: AXI4MasterParameters) = m.copy(aligned = true)
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val node = AXI4AdapterNode(
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masterFn = { mp => mp.copy(masters = mp.masters.map(m => mapMaster(m)), userBits = mp.userBits + 1) },
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slaveFn = { sp => sp.copy(slaves = sp.slaves .map(s => mapSlave(s, sp.beatBytes))) })
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val slave = edgeOut.slave
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val slaves = slave.slaves
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val beatBytes = slave.beatBytes
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val lgBytes = log2Ceil(beatBytes)
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val master = edgeIn.master
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val masters = master.masters
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// We don't support fragmenting to sub-beat accesses
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slaves.foreach { s =>
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require (!s.supportsRead || s.supportsRead.contains(beatBytes))
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require (!s.supportsWrite || s.supportsWrite.contains(beatBytes))
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}
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/* We need to decompose a request into
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* FIXED => each beat is a new request
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* WRAP/INCR => take xfr up to next power of two, capped by max size of target
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*
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* On AR and AW, we fragment one request into many
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* On W we set 'last' on beats which are fragment boundaries
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* On R we clear 'last' on the fragments being reassembled
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* On B we clear 'valid' on the responses for the injected fragments
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*
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* AR=>R and AW+W=>B are completely independent state machines.
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*/
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/* Returns the number of beats to execute and the new address */
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def fragment(a: IrrevocableIO[AXI4BundleA], supportedSizes1: Seq[Int]): (IrrevocableIO[AXI4BundleA], Bool, UInt) = {
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val out = Wire(a)
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val busy = RegInit(Bool(false))
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val r_addr = Reg(UInt(width = a.bits.params.addrBits))
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val r_len = Reg(UInt(width = AXI4Parameters.lenBits))
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val len = Mux(busy, r_len, a.bits.len)
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val addr = Mux(busy, r_addr, a.bits.addr)
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val lo = if (lgBytes == 0) UInt(0) else addr(lgBytes-1, 0)
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val hi = addr >> lgBytes
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val alignment = hi(AXI4Parameters.lenBits-1,0)
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// We don't care about illegal addresses; bursts or no bursts... whatever circuit is simpler (AXI4ToTL will fix it)
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val sizes1 = (supportedSizes1 zip slave.slaves.map(_.address)).filter(_._1 >= 0).groupBy(_._1).mapValues(_.flatMap(_._2))
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val reductionMask = AddressDecoder(sizes1.values.toList)
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val support1 = Mux1H(sizes1.toList.map { case (v, a) => // maximum supported size-1 based on target address
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(AddressSet.unify(a.map(_.widen(~reductionMask)).distinct).map(_.contains(addr)).reduce(_||_), UInt(v))
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})
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/* We need to compute the largest transfer allowed by the AXI len.
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* len+1 is the number of beats to execute.
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* We want the MSB(len+1)-1; one less than the largest power of two we could execute.
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* There are two cases; either len is 2^n-1 in which case we leave it unchanged, ELSE
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* fill the bits from highest to lowest, and shift right by one bit.
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*/
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val fillLow = rightOR(len) >> 1 // set all bits in positions < a set bit
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val wipeHigh = ~leftOR(~len) // clear all bits in position >= a cleared bit
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val remain1 = fillLow | wipeHigh // MSB(a.len+1)-1
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val align1 = ~leftOR(alignment) // transfer size limited by address alignment
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val maxSupported1 = remain1 & align1 & support1 // Take the minimum of all the limits
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// Things that cause us to degenerate to a single beat
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val fixed = a.bits.burst === AXI4Parameters.BURST_FIXED
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val narrow = a.bits.size =/= UInt(lgBytes)
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val bad = fixed || narrow
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// The number of beats-1 to execute
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val beats1 = Mux(bad, UInt(0), maxSupported1)
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val beats = OH1ToOH(beats1) // beats1 + 1
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val inc_addr = addr + (beats << a.bits.size) // address after adding transfer
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val wrapMask = a.bits.bytes1() // only these bits may change, if wrapping
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val mux_addr = Wire(init = inc_addr)
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when (a.bits.burst === AXI4Parameters.BURST_WRAP) {
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mux_addr := (inc_addr & wrapMask) | ~(~a.bits.addr | wrapMask)
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}
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when (a.bits.burst === AXI4Parameters.BURST_FIXED) {
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mux_addr := a.bits.addr
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}
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val last = beats1 === len
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a.ready := out.ready && last
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out.valid := a.valid
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out.bits := a.bits
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out.bits.len := beats1
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// We forcibly align every access. If the first beat was misaligned, the strb bits
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// for the lower addresses must not have been set. Therefore, rounding the address
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// down is harmless. We can do this after the address update algorithm, because the
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// incremented values will be rounded down the same way. Furthermore, a subword
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// offset cannot cause a premature wrap-around.
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out.bits.addr := ~(~addr | UIntToOH1(a.bits.size, lgBytes))
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when (out.fire()) {
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busy := !last
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r_addr := mux_addr
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r_len := len - beats
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}
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(out, last, beats)
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}
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// The size to which we will fragment the access
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val readSizes1 = slaves.map(s => s.supportsRead .max/beatBytes-1)
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val writeSizes1 = slaves.map(s => s.supportsWrite.max/beatBytes-1)
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// Irrevocable queues in front because we want to accept the request before responses come back
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val (in_ar, ar_last, _) = fragment(Queue.irrevocable(in.ar, 1, flow=true), readSizes1)
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val (in_aw, aw_last, w_beats) = fragment(Queue.irrevocable(in.aw, 1, flow=true), writeSizes1)
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// AXI ready may not depend on valid of other channels
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// We cut wready here along with awready and arready before AXI4ToTL
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val in_w = Queue.irrevocable(in.w, 1, flow=true)
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// AR flow control; super easy
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out.ar <> in_ar
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out.ar.bits.user.get := Cat(in_ar.bits.user.toList ++ Seq(ar_last))
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// When does W channel start counting a new transfer
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val wbeats_latched = RegInit(Bool(false))
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val wbeats_ready = Wire(Bool())
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val wbeats_valid = Wire(Bool())
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when (wbeats_valid && wbeats_ready) { wbeats_latched := Bool(true) }
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when (out.aw.fire()) { wbeats_latched := Bool(false) }
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// AW flow control
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out.aw.valid := in_aw.valid && (wbeats_ready || wbeats_latched)
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in_aw.ready := out.aw.ready && (wbeats_ready || wbeats_latched)
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wbeats_valid := in_aw.valid && !wbeats_latched
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out.aw.bits := in_aw.bits
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out.aw.bits.user.get := Cat(in_aw.bits.user.toList ++ Seq(aw_last))
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// We need to inject 'last' into the W channel fragments, count!
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val w_counter = RegInit(UInt(0, width = AXI4Parameters.lenBits+1))
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val w_idle = w_counter === UInt(0)
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val w_todo = Mux(w_idle, Mux(wbeats_valid, w_beats, UInt(0)), w_counter)
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val w_last = w_todo === UInt(1)
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w_counter := w_todo - out.w.fire()
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assert (!out.w.fire() || w_todo =/= UInt(0)) // underflow impossible
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// W flow control
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wbeats_ready := w_idle
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out.w.valid := in_w.valid && (!wbeats_ready || wbeats_valid)
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in_w.ready := out.w.ready && (!wbeats_ready || wbeats_valid)
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out.w.bits := in_w.bits
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out.w.bits.last := w_last
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// We should also recreate the last last
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assert (!out.w.valid || !in_w.bits.last || w_last)
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// R flow control
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val r_last = out.r.bits.user.get(0)
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in.r <> out.r
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in.r.bits.last := out.r.bits.last && r_last
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in.r.bits.user.foreach { _ := out.r.bits.user.get >> 1 }
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// B flow control
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val b_last = out.b.bits.user.get(0)
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in.b <> out.b
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in.b.valid := out.b.valid && b_last
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out.b.ready := in.b.ready || !b_last
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in.b.bits.user.foreach { _ := out.b.bits.user.get >> 1 }
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// Merge errors from dropped B responses
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val error = RegInit(Vec.fill(edgeIn.master.endId) { UInt(0, width = AXI4Parameters.respBits)})
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in.b.bits.resp := out.b.bits.resp | error(out.b.bits.id)
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(error zip UIntToOH(out.b.bits.id, edgeIn.master.endId).toBools) foreach { case (reg, sel) =>
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when (sel && out.b.fire()) { reg := Mux(b_last, UInt(0), reg | out.b.bits.resp) }
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}
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}
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}
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}
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object AXI4Fragmenter
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{
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def apply()(implicit p: Parameters): AXI4Node =
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{
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val axi4frag = LazyModule(new AXI4Fragmenter)
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axi4frag.node
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}
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}
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