67 lines
2.5 KiB
Scala
67 lines
2.5 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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class AXI4Filter(
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Sfilter: AXI4SlaveParameters => Option[AXI4SlaveParameters] = AXI4Filter.Sidentity,
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Mfilter: AXI4MasterParameters => Option[AXI4MasterParameters] = AXI4Filter.Midentity
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)(implicit p: Parameters) extends LazyModule
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{
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val node = AXI4AdapterNode(
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slaveFn = { sp => sp.copy(slaves = sp.slaves.flatMap { s =>
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val out = Sfilter(s)
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out.foreach { o => // Confirm the filter only REMOVES capability
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o.address.foreach { a => require (s.address.map(_.contains(a)).reduce(_||_)) }
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require (o.regionType <= s.regionType)
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// we allow executable to be changed both ways
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require (s.supportsWrite.contains(o.supportsWrite))
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require (s.supportsRead .contains(o.supportsRead))
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require (!o.interleavedId.isDefined || s.interleavedId == o.interleavedId)
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}
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out
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})},
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masterFn = { mp => mp.copy(masters = mp.masters.flatMap { m =>
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val out = Mfilter(m)
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out.foreach { o => require (m.id.contains(o.id)) }
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out
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})})
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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out <> in
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}
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}
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}
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object AXI4Filter
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{
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def Midentity: AXI4MasterParameters => Option[AXI4MasterParameters] = { m => Some(m) }
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def Sidentity: AXI4SlaveParameters => Option[AXI4SlaveParameters] = { s => Some(s) }
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def Smask(select: AddressSet): AXI4SlaveParameters => Option[AXI4SlaveParameters] = { s =>
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val filtered = s.address.map(_.intersect(select)).flatten
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val alignment = select.alignment /* alignment 0 means 'select' selected everything */
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val maxTransfer = 1 << 30
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val capTransfer = if (alignment == 0 || alignment > maxTransfer) maxTransfer else alignment.toInt
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val cap = TransferSizes(1, capTransfer)
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if (filtered.isEmpty) { None } else {
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Some(s.copy(
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address = filtered,
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supportsWrite = s.supportsWrite.intersect(cap),
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supportsRead = s.supportsRead .intersect(cap)))
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}
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}
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def apply(
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Sfilter: AXI4SlaveParameters => Option[AXI4SlaveParameters] = AXI4Filter.Sidentity,
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Mfilter: AXI4MasterParameters => Option[AXI4MasterParameters] = AXI4Filter.Midentity
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)(implicit p: Parameters): AXI4Node =
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{
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val axi4filt = LazyModule(new AXI4Filter(Sfilter, Mfilter))
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axi4filt.node
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}
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}
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