100 lines
3.5 KiB
Scala
100 lines
3.5 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util.UIntToOH1
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class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) extends LazyModule
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{
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val node = AXI4AdapterNode(
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masterFn = { mp => mp.copy(
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userBits = 0,
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masters = mp.masters.map { m => m.copy(
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maxFlight = (m.maxFlight, capMaxFlight) match {
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case (Some(x), Some(y)) => Some(x min y)
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case (Some(x), None) => Some(x)
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case (None, Some(y)) => Some(y)
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case (None, None) => None })})},
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slaveFn = { sp => sp })
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val bits = edgeIn.bundle.userBits
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val need_bypass = edgeOut.slave.minLatency < 1
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require (bits > 0) // useless UserYanker!
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edgeOut.master.masters.foreach { m =>
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require (m.maxFlight.isDefined, "UserYanker needs a flight cap on each ID")
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}
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def queue(id: Int) = {
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val depth = edgeOut.master.masters.find(_.id.contains(id)).flatMap(_.maxFlight).getOrElse(0)
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if (depth == 0) {
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Wire(new QueueIO(UInt(width = bits), 1)) // unused ID => undefined value
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} else {
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Module(new Queue(UInt(width = bits), depth, flow=need_bypass)).io
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}
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}
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val rqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) }
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val wqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) }
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val arid = in.ar.bits.id
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val ar_ready = Vec(rqueues.map(_.enq.ready))(arid)
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in .ar.ready := out.ar.ready && ar_ready
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out.ar.valid := in .ar.valid && ar_ready
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out.ar.bits := in .ar.bits
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val rid = out.r.bits.id
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val r_valid = Vec(rqueues.map(_.deq.valid))(rid)
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val r_bits = Vec(rqueues.map(_.deq.bits))(rid)
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assert (!out.r.valid || r_valid) // Q must be ready faster than the response
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in.r <> out.r
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in.r.bits.user.get := r_bits
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val arsel = UIntToOH(arid, edgeIn.master.endId).toBools
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val rsel = UIntToOH(rid, edgeIn.master.endId).toBools
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(rqueues zip (arsel zip rsel)) foreach { case (q, (ar, r)) =>
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q.deq.ready := out.r .valid && in .r .ready && r && out.r.bits.last
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q.enq.valid := in .ar.valid && out.ar.ready && ar
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q.enq.bits := in.ar.bits.user.get
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}
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val awid = in.aw.bits.id
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val aw_ready = Vec(wqueues.map(_.enq.ready))(awid)
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in .aw.ready := out.aw.ready && aw_ready
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out.aw.valid := in .aw.valid && aw_ready
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out.aw.bits := in .aw.bits
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val bid = out.b.bits.id
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val b_valid = Vec(wqueues.map(_.deq.valid))(bid)
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val b_bits = Vec(wqueues.map(_.deq.bits))(bid)
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assert (!out.b.valid || b_valid) // Q must be ready faster than the response
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in.b <> out.b
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in.b.bits.user.get := b_bits
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val awsel = UIntToOH(awid, edgeIn.master.endId).toBools
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val bsel = UIntToOH(bid, edgeIn.master.endId).toBools
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(wqueues zip (awsel zip bsel)) foreach { case (q, (aw, b)) =>
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q.deq.ready := out.b .valid && in .b .ready && b
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q.enq.valid := in .aw.valid && out.aw.ready && aw
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q.enq.bits := in.aw.bits.user.get
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}
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out.w <> in.w
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}
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}
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}
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object AXI4UserYanker
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{
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def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node =
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{
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val axi4yank = LazyModule(new AXI4UserYanker(capMaxFlight))
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axi4yank.node
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}
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}
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