84 lines
2.7 KiB
Scala
84 lines
2.7 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import scala.math.{min,max}
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class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
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{
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require (idBits >= 0)
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val node = AXI4AdapterNode(
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masterFn = { mp =>
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// Create one new "master" per ID
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val masters = Array.tabulate(1 << idBits) { i => AXI4MasterParameters(
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name = "",
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id = IdRange(i, i+1),
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aligned = true,
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maxFlight = Some(0))
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}
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// Accumluate the names of masters we squish
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val names = Array.fill(1 << idBits) { new scala.collection.mutable.HashSet[String]() }
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// Squash the information from original masters into new ID masters
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mp.masters.foreach { m =>
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for (i <- m.id.start until m.id.end) {
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val j = i % (1 << idBits)
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val old = masters(j)
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names(j) += m.name
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masters(j) = old.copy(
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aligned = old.aligned && m.aligned,
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maxFlight = old.maxFlight.flatMap { o => m.maxFlight.map { n => o+n } })
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}
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}
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mp.copy(
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userBits = mp.userBits + max(0, log2Ceil(mp.endId) - idBits),
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masters = masters.zipWithIndex.map { case (m,i) => m.copy(name = names(i).toList.mkString(", "))})
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},
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slaveFn = { sp => sp
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})
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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// Leave everything mostly untouched
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out.ar <> in.ar
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out.aw <> in.aw
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out.w <> in.w
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in.b <> out.b
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in.r <> out.r
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val bits = log2Ceil(edgeIn.master.endId) - idBits
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if (bits > 0) {
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// (in.aX.bits.id >> idBits).width = bits > 0
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out.ar.bits.user.get := Cat(in.ar.bits.user.toList ++ Seq(in.ar.bits.id >> idBits))
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out.aw.bits.user.get := Cat(in.aw.bits.user.toList ++ Seq(in.aw.bits.id >> idBits))
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// user.isDefined => width > 0
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in.r.bits.user.foreach { _ := out.r.bits.user.get >> bits }
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in.b.bits.user.foreach { _ := out.b.bits.user.get >> bits }
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// Special care is needed in case of 0 idBits, b/c .id has width 1 still
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if (idBits == 0) {
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out.ar.bits.id := UInt(0)
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out.aw.bits.id := UInt(0)
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in.r.bits.id := out.r.bits.user.get
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in.b.bits.id := out.b.bits.user.get
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} else {
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in.r.bits.id := Cat(out.r.bits.user.get, out.r.bits.id)
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in.b.bits.id := Cat(out.b.bits.user.get, out.b.bits.id)
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}
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}
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}
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}
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}
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object AXI4IdIndexer
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{
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def apply(idBits: Int)(implicit p: Parameters): AXI4Node =
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{
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val axi4index = LazyModule(new AXI4IdIndexer(idBits))
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axi4index.node
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}
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}
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