2014-09-13 03:06:41 +02:00
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// See LICENSE for license details.
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2012-02-26 02:09:26 +01:00
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package rocket
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2011-10-26 08:02:47 +02:00
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2012-10-08 07:37:29 +02:00
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import Chisel._
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2012-11-18 02:24:08 +01:00
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import Util._
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2014-09-01 22:28:58 +02:00
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import uncore._
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2011-10-26 08:02:47 +02:00
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2014-08-08 21:23:02 +02:00
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case object BuildFPU extends Field[Option[() => FPU]]
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2015-02-02 05:04:13 +01:00
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case object XLen extends Field[Int]
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2014-09-01 22:28:58 +02:00
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case object NMultXpr extends Field[Int]
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2014-09-17 23:24:03 +02:00
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case object FetchWidth extends Field[Int]
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2014-09-01 22:28:58 +02:00
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case object RetireWidth extends Field[Int]
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case object UseVM extends Field[Boolean]
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case object FastLoadWord extends Field[Boolean]
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case object FastLoadByte extends Field[Boolean]
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case object FastMulDiv extends Field[Boolean]
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case object CoreInstBits extends Field[Int]
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case object CoreDataBits extends Field[Int]
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case object CoreDCacheReqTagBits extends Field[Int]
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2015-03-25 07:48:47 +01:00
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case object NCustomMRWCSRs extends Field[Int]
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2014-09-01 22:28:58 +02:00
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abstract trait CoreParameters extends UsesParameters {
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2015-02-02 05:04:13 +01:00
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val xLen = params(XLen)
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val paddrBits = params(PAddrBits)
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val vaddrBits = params(VAddrBits)
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val pgIdxBits = params(PgIdxBits)
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val ppnBits = params(PPNBits)
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val vpnBits = params(VPNBits)
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2015-03-28 00:20:59 +01:00
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val pgLevels = params(PgLevels)
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val pgLevelBits = params(PgLevelBits)
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2015-02-02 05:04:13 +01:00
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val asIdBits = params(ASIdBits)
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val retireWidth = params(RetireWidth)
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2014-09-17 23:24:03 +02:00
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val coreFetchWidth = params(FetchWidth)
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2014-09-01 22:28:58 +02:00
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val coreInstBits = params(CoreInstBits)
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val coreInstBytes = coreInstBits/8
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2015-02-02 05:04:13 +01:00
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val coreDataBits = xLen
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2014-09-01 22:28:58 +02:00
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val coreDataBytes = coreDataBits/8
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val coreDCacheReqTagBits = params(CoreDCacheReqTagBits)
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2015-02-02 05:04:13 +01:00
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val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits
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2014-09-01 22:28:58 +02:00
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if(params(FastLoadByte)) require(params(FastLoadWord))
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2014-09-26 03:52:58 +02:00
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}
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abstract trait RocketCoreParameters extends CoreParameters
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{
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2014-09-17 23:24:03 +02:00
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require(params(FetchWidth) == 1) // for now...
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2014-09-01 22:28:58 +02:00
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require(params(RetireWidth) == 1) // for now...
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}
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2014-09-26 03:52:58 +02:00
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2014-09-01 22:28:58 +02:00
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abstract class CoreBundle extends Bundle with CoreParameters
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abstract class CoreModule extends Module with CoreParameters
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2014-08-02 03:01:08 +02:00
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2014-08-08 21:23:02 +02:00
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class RocketIO extends Bundle
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2011-10-26 08:02:47 +02:00
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{
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2014-08-08 21:23:02 +02:00
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val host = new HTIFIO
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val imem = new CPUFrontendIO
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val dmem = new HellaCacheIO
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val ptw = new DatapathPTWIO().flip
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2013-09-15 00:31:50 +02:00
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val rocc = new RoCCInterface().flip
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2011-10-26 08:02:47 +02:00
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}
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2014-09-01 22:28:58 +02:00
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class Core extends Module with CoreParameters
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2011-10-26 08:02:47 +02:00
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{
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2014-08-08 21:23:02 +02:00
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val io = new RocketIO
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2011-11-09 23:52:17 +01:00
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2014-08-08 21:23:02 +02:00
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val ctrl = Module(new Control)
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2013-08-12 19:39:11 +02:00
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val dpath = Module(new Datapath)
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2011-10-26 08:02:47 +02:00
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2014-09-01 22:28:58 +02:00
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//If so specified, build an FPU module and wire it in
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params(BuildFPU)
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2014-09-08 02:54:41 +02:00
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.map { bf => bf() }
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2014-09-01 22:28:58 +02:00
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.foreach { fpu =>
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dpath.io.fpu <> fpu.io.dpath
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ctrl.io.fpu <> fpu.io.ctrl
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}
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2013-09-15 00:31:50 +02:00
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2012-11-06 17:13:44 +01:00
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ctrl.io.dpath <> dpath.io.ctrl
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dpath.io.host <> io.host
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ctrl.io.imem <> io.imem
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dpath.io.imem <> io.imem
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2013-09-13 07:34:38 +02:00
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ctrl.io.dmem <> io.dmem
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dpath.io.dmem <> io.dmem
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2011-11-09 23:52:17 +01:00
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2013-09-13 07:34:38 +02:00
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dpath.io.ptw <> io.ptw
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2012-11-06 17:13:44 +01:00
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2013-09-15 00:31:50 +02:00
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ctrl.io.rocc <> io.rocc
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dpath.io.rocc <> io.rocc
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2011-10-26 08:02:47 +02:00
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}
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