riscv/rocket-chip
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rocket-chip/rocket/src/main/scala/cpu.scala

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change package name and sbt project name to rocket
2012-02-26 02:09:26 +01:00
package rocket
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
integrating ITLB & PTW
2011-11-09 23:52:17 +01:00
import Chisel._;
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
import Node._;
import Constants._;
initial vu integration
2012-02-09 06:43:45 +01:00
import hwacha._
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
class ioRocket extends Bundle()
{
Refactored cpu/cache interface to use nested bundles
2012-05-02 03:23:04 +02:00
val host = new ioHTIF
val imem = (new ioImem).flip
val vimem = (new ioImem).flip
val dmem = new ioHellaCache
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
decouple all interfaces between tile and top also, add an "incoherent" bit to tilelink to indicate no probes needed
2012-07-18 07:55:00 +02:00
class rocketProc extends Component
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
{
Refactored cpu/cache interface to use nested bundles
2012-05-02 03:23:04 +02:00
val io = new ioRocket
integrating ITLB & PTW
2011-11-09 23:52:17 +01:00
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
val ctrl = new rocketCtrl();
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
val dpath = new rocketDpath();
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
more tlb/ptw fixes
2011-11-10 09:23:29 +01:00
val dtlb = new rocketDTLB(DTLB_ENTRIES);
integrating ITLB & PTW
2011-11-09 23:52:17 +01:00
val itlb = new rocketITLB(ITLB_ENTRIES);
generalize page table walker also, don't instantiate vitlb when !HAVE_VEC
2012-05-03 11:29:09 +02:00
val ptw = new rocketPTW(if (HAVE_VEC) 3 else 2)
Refactored cpu/cache interface to use nested bundles
2012-05-02 03:23:04 +02:00
val arb = new rocketHellaCacheArbiter(DCACHE_PORTS)
integrating ITLB & PTW
2011-11-09 23:52:17 +01:00
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-26 07:05:30 +01:00
var vu: vu = null
if (HAVE_VEC)
{
vu = new vu()
// cpu, vector prefetch, and vector use the DTLB
change the tlb arbiter to a round robing one
2012-03-20 23:21:36 +01:00
val dtlbarb = new RRArbiter(3)({new ioDTLB_CPU_req_bundle()})
moving util out into Chisel standard library
2012-06-06 21:47:17 +02:00
val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2Up(3)))
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-26 07:05:30 +01:00
when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen }
small changes to the dtlb arbiter
2012-02-27 01:19:50 +01:00
// tlb respones come out a cycle later
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-26 07:05:30 +01:00
val chosen_vec = dtlbchosen === Bits(DTLB_VEC)
val chosen_pf = dtlbchosen === Bits(DTLB_VPF)
val chosen_cpu = dtlbchosen === Bits(DTLB_CPU)
small changes to the dtlb arbiter
2012-02-27 01:19:50 +01:00
dtlbarb.io.in(DTLB_VEC) <> vu.io.vec_tlb_req
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-26 07:05:30 +01:00
vu.io.vec_tlb_resp.xcpt_ld := chosen_vec && dtlb.io.cpu_resp.xcpt_ld
vu.io.vec_tlb_resp.xcpt_st := chosen_vec && dtlb.io.cpu_resp.xcpt_st
add pf fault handling
2012-03-18 23:06:39 +01:00
vu.io.vec_tlb_resp.xcpt_pf := Bool(false)
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-26 07:05:30 +01:00
vu.io.vec_tlb_resp.miss := chosen_vec && dtlb.io.cpu_resp.miss
vu.io.vec_tlb_resp.ppn := dtlb.io.cpu_resp.ppn
small changes to the dtlb arbiter
2012-02-27 01:19:50 +01:00
dtlbarb.io.in(DTLB_VPF) <> vu.io.vec_pftlb_req
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-26 07:05:30 +01:00
vu.io.vec_pftlb_resp.xcpt_ld := Bool(false)
vu.io.vec_pftlb_resp.xcpt_st := Bool(false)
add pf fault handling
2012-03-18 23:06:39 +01:00
vu.io.vec_pftlb_resp.xcpt_pf := chosen_pf && dtlb.io.cpu_resp.xcpt_pf
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-26 07:05:30 +01:00
vu.io.vec_pftlb_resp.miss := chosen_pf && dtlb.io.cpu_resp.miss
vu.io.vec_pftlb_resp.ppn := dtlb.io.cpu_resp.ppn
// connect DTLB to ctrl+dpath
dtlbarb.io.in(DTLB_CPU).valid := ctrl.io.dtlb_val
dtlbarb.io.in(DTLB_CPU).bits.kill := ctrl.io.dtlb_kill
Refactored cpu/cache interface to use nested bundles
2012-05-02 03:23:04 +02:00
dtlbarb.io.in(DTLB_CPU).bits.cmd := ctrl.io.dmem.req.bits.cmd
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-26 07:05:30 +01:00
dtlbarb.io.in(DTLB_CPU).bits.asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
simplify cpu-cache interface
2012-02-27 03:26:29 +01:00
dtlbarb.io.in(DTLB_CPU).bits.vpn := dpath.io.dtlb.vpn
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-26 07:05:30 +01:00
ctrl.io.dtlb_rdy := dtlbarb.io.in(DTLB_CPU).ready
ctrl.io.xcpt_dtlb_ld := chosen_cpu && dtlb.io.cpu_resp.xcpt_ld
ctrl.io.xcpt_dtlb_st := chosen_cpu && dtlb.io.cpu_resp.xcpt_st
ctrl.io.dtlb_miss := chosen_cpu && dtlb.io.cpu_resp.miss
dtlb.io.cpu_req <> dtlbarb.io.out
}
else
{
// connect DTLB to ctrl+dpath
dtlb.io.cpu_req.valid := ctrl.io.dtlb_val
dtlb.io.cpu_req.bits.kill := ctrl.io.dtlb_kill
Refactored cpu/cache interface to use nested bundles
2012-05-02 03:23:04 +02:00
dtlb.io.cpu_req.bits.cmd := ctrl.io.dmem.req.bits.cmd
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-26 07:05:30 +01:00
dtlb.io.cpu_req.bits.asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
simplify cpu-cache interface
2012-02-27 03:26:29 +01:00
dtlb.io.cpu_req.bits.vpn := dpath.io.dtlb.vpn
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-26 07:05:30 +01:00
ctrl.io.xcpt_dtlb_ld := dtlb.io.cpu_resp.xcpt_ld
ctrl.io.xcpt_dtlb_st := dtlb.io.cpu_resp.xcpt_st
ctrl.io.dtlb_rdy := dtlb.io.cpu_req.ready
ctrl.io.dtlb_miss := dtlb.io.cpu_resp.miss
}
dtlb.io.invalidate := dpath.io.ptbr_wen
dtlb.io.status := dpath.io.ctrl.status
Refactored cpu/cache interface to use nested bundles
2012-05-02 03:23:04 +02:00
arb.io.requestor(DMEM_CPU).req.bits.ppn := dtlb.io.cpu_resp.ppn
ctrl.io.dmem.req.ready := dtlb.io.cpu_req.ready && arb.io.requestor(DMEM_CPU).req.ready
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-26 07:05:30 +01:00
// connect page table walker to TLBs, page table base register (from PCR)
// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
generalize page table walker also, don't instantiate vitlb when !HAVE_VEC
2012-05-03 11:29:09 +02:00
ptw.io.requestor(0) <> itlb.io.ptw
ptw.io.requestor(1) <> dtlb.io.ptw
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-26 07:05:30 +01:00
ptw.io.ptbr := dpath.io.ptbr;
Refactored cpu/cache interface to use nested bundles
2012-05-02 03:23:04 +02:00
arb.io.requestor(DMEM_PTW) <> ptw.io.mem
arb.io.mem <> io.dmem
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-26 07:05:30 +01:00
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
ctrl.io.dpath <> dpath.io.ctrl;
Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
2012-01-23 18:51:35 +01:00
dpath.io.host <> io.host;
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
updated riscv-bmarks and riscv-tests to build with new toolchain
2011-11-15 09:11:22 +01:00
// FIXME: try to make this more compact
cleanup before adding dtlb
2011-11-10 08:27:29 +01:00
// connect ITLB to I$, ctrl, dpath
updated riscv-bmarks and riscv-tests to build with new toolchain
2011-11-15 09:11:22 +01:00
itlb.io.cpu.invalidate := dpath.io.ptbr_wen;
integrating ITLB & PTW
2011-11-09 23:52:17 +01:00
itlb.io.cpu.status := dpath.io.ctrl.status;
cleanup before adding dtlb
2011-11-10 08:27:29 +01:00
itlb.io.cpu.req_val := ctrl.io.imem.req_val;
integrating ITLB & PTW
2011-11-09 23:52:17 +01:00
itlb.io.cpu.req_asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
check pc/effective address sign extension
2012-01-24 09:15:17 +01:00
itlb.io.cpu.req_vpn := dpath.io.imem.req_addr(VADDR_BITS,PGIDX_BITS);
more tlb/ptw debugging
2011-11-12 09:25:06 +01:00
io.imem.req_idx := dpath.io.imem.req_addr(PGIDX_BITS-1,0);
io.imem.req_ppn := itlb.io.cpu.resp_ppn;
io.imem.req_val := ctrl.io.imem.req_val;
make BTB fully associative; don't use it for JALR JALR created a long path from the ALU in execute stage to an address comparator to the next-PC mux. the benfit was close to nil, anyway.
2012-02-09 10:32:52 +01:00
io.imem.invalidate := ctrl.io.dpath.flush_inst;
integrating ITLB & PTW
2011-11-09 23:52:17 +01:00
ctrl.io.imem.resp_val := io.imem.resp_val;
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
dpath.io.imem.resp_data := io.imem.resp_data;
ctrl.io.xcpt_itlb := itlb.io.cpu.exception;
more tlb/ptw debugging
2011-11-12 09:25:06 +01:00
io.imem.itlb_miss := itlb.io.cpu.resp_miss;
updated itlb
2011-11-12 03:48:34 +01:00
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
// connect arbiter to ctrl+dpath+DTLB
Removed defunct ioDmem
2012-05-08 02:28:18 +02:00
//TODO: views on nested bundles?
Refactored cpu/cache interface to use nested bundles
2012-05-02 03:23:04 +02:00
arb.io.requestor(DMEM_CPU).resp <> ctrl.io.dmem.resp
arb.io.requestor(DMEM_CPU).xcpt <> ctrl.io.dmem.xcpt
arb.io.requestor(DMEM_CPU).resp <> dpath.io.dmem.resp
arb.io.requestor(DMEM_CPU).req.valid := ctrl.io.dmem.req.valid
ctrl.io.dmem.req.ready := arb.io.requestor(DMEM_CPU).req.ready
arb.io.requestor(DMEM_CPU).req.bits.kill := ctrl.io.dmem.req.bits.kill
arb.io.requestor(DMEM_CPU).req.bits.cmd := ctrl.io.dmem.req.bits.cmd
arb.io.requestor(DMEM_CPU).req.bits.typ := ctrl.io.dmem.req.bits.typ
arb.io.requestor(DMEM_CPU).req.bits.idx := dpath.io.dmem.req.bits.idx
arb.io.requestor(DMEM_CPU).req.bits.tag := dpath.io.dmem.req.bits.tag
arb.io.requestor(DMEM_CPU).req.bits.data := dpath.io.dmem.req.bits.data
more tlb/ptw fixes
2011-11-10 09:23:29 +01:00
expose FMA ports outside of FPU (for the VU)
2012-02-24 02:39:34 +01:00
var fpu: rocketFPU = null
add fp loads/stores
2012-02-08 08:54:25 +01:00
if (HAVE_FPU)
{
expose FMA ports outside of FPU (for the VU)
2012-02-24 02:39:34 +01:00
fpu = new rocketFPU(4,6)
add fp loads/stores
2012-02-08 08:54:25 +01:00
dpath.io.fpu <> fpu.io.dpath
WIP on FPU
2012-02-12 13:36:01 +01:00
ctrl.io.fpu <> fpu.io.ctrl
add fp loads/stores
2012-02-08 08:54:25 +01:00
}
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
initial vu integration
2012-02-09 06:43:45 +01:00
if (HAVE_VEC)
{
refactor vector control logic & datapath in the rocket core
2012-02-15 22:30:22 +01:00
dpath.io.vec_ctrl <> ctrl.io.vec_dpath
// hooking up vector I$
generalize page table walker also, don't instantiate vitlb when !HAVE_VEC
2012-05-03 11:29:09 +02:00
val vitlb = new rocketITLB(VITLB_ENTRIES)
ptw.io.requestor(2) <> vitlb.io.ptw
hwacha integration: now it compiles correctly!
2012-02-15 08:34:57 +01:00
vitlb.io.cpu.invalidate := dpath.io.ptbr_wen
vitlb.io.cpu.status := dpath.io.ctrl.status
vitlb.io.cpu.req_val := vu.io.imem_req.valid
vitlb.io.cpu.req_asid := Bits(0,ASID_BITS) // FIXME: connect to PCR
vitlb.io.cpu.req_vpn := vu.io.imem_req.bits(VADDR_BITS,PGIDX_BITS).toUFix
io.vimem.req_idx := vu.io.imem_req.bits(PGIDX_BITS-1,0)
io.vimem.req_ppn := vitlb.io.cpu.resp_ppn
io.vimem.req_val := vu.io.imem_req.valid
io.vimem.invalidate := ctrl.io.dpath.flush_inst
vector-vector add working!
2012-02-15 11:28:07 +01:00
vu.io.imem_req.ready := Bool(true)
hwacha integration: now it compiles correctly!
2012-02-15 08:34:57 +01:00
vu.io.imem_resp.valid := io.vimem.resp_val
vu.io.imem_resp.bits := io.vimem.resp_data
add vitlb exception port
2012-03-17 22:03:33 +01:00
vu.io.vitlb_exception := vitlb.io.cpu.exception
hwacha integration: now it compiles correctly!
2012-02-15 08:34:57 +01:00
io.vimem.itlb_miss := vitlb.io.cpu.resp_miss
refactor vector control logic & datapath in the rocket core
2012-02-15 22:30:22 +01:00
// hooking up vector command queues
vu.io.vec_cmdq.valid := ctrl.io.vec_iface.vcmdq_valid
vu.io.vec_cmdq.bits := dpath.io.vec_iface.vcmdq_bits
vu.io.vec_ximm1q.valid := ctrl.io.vec_iface.vximm1q_valid
vu.io.vec_ximm1q.bits := dpath.io.vec_iface.vximm1q_bits
vu.io.vec_ximm2q.valid := ctrl.io.vec_iface.vximm2q_valid
vu.io.vec_ximm2q.bits := dpath.io.vec_iface.vximm2q_bits
refactor code related to vector exceptions - revisied interfaces - new instructions
2012-03-04 00:09:42 +01:00
vu.io.vec_cntq.valid := ctrl.io.vec_iface.vcntq_valid
changes to xcpt handling
2012-03-18 01:50:37 +01:00
vu.io.vec_cntq.bits := Cat(dpath.io.vec_iface.vcntq_last, dpath.io.vec_iface.vcntq_bits)
refactor vector control logic & datapath in the rocket core
2012-02-15 22:30:22 +01:00
added prefetch queues for vu
2012-02-24 09:44:13 +01:00
// prefetch queues
vu.io.vec_pfcmdq.valid := ctrl.io.vec_iface.vpfcmdq_valid
vu.io.vec_pfcmdq.bits := dpath.io.vec_iface.vcmdq_bits
vu.io.vec_pfximm1q.valid := ctrl.io.vec_iface.vpfximm1q_valid
vu.io.vec_pfximm1q.bits := dpath.io.vec_iface.vximm1q_bits
vu.io.vec_pfximm2q.valid := ctrl.io.vec_iface.vpfximm2q_valid
vu.io.vec_pfximm2q.bits := dpath.io.vec_iface.vximm2q_bits
add prefetch count queue
2012-03-05 21:09:41 +01:00
vu.io.vec_pfcntq.valid := ctrl.io.vec_iface.vpfcntq_valid
vu.io.vec_pfcntq.bits := dpath.io.vec_iface.vcntq_bits
added prefetch queues for vu
2012-02-24 09:44:13 +01:00
// don't have to use pf ready signals
// if cmdq is not a load or store
refactor vector control logic & datapath in the rocket core
2012-02-15 22:30:22 +01:00
ctrl.io.vec_iface.vcmdq_ready := vu.io.vec_cmdq.ready
ctrl.io.vec_iface.vximm1q_ready := vu.io.vec_ximm1q.ready
ctrl.io.vec_iface.vximm2q_ready := vu.io.vec_ximm2q.ready
refactor code related to vector exceptions - revisied interfaces - new instructions
2012-03-04 00:09:42 +01:00
ctrl.io.vec_iface.vcntq_ready := vu.io.vec_cntq.ready
added prefetch queues for vu
2012-02-24 09:44:13 +01:00
ctrl.io.vec_iface.vpfcmdq_ready := vu.io.vec_pfcmdq.ready
ctrl.io.vec_iface.vpfximm1q_ready := vu.io.vec_pfximm1q.ready
ctrl.io.vec_iface.vpfximm2q_ready := vu.io.vec_pfximm2q.ready
add prefetch count queue
2012-03-05 21:09:41 +01:00
ctrl.io.vec_iface.vpfcntq_ready := vu.io.vec_pfcntq.ready
refactor code related to vector exceptions - revisied interfaces - new instructions
2012-03-04 00:09:42 +01:00
changes to the vector exception interface
2012-03-12 05:38:47 +01:00
// user level vector command queue ready signals
ctrl.io.vec_iface.vcmdq_user_ready := vu.io.vec_cmdq_user_ready
ctrl.io.vec_iface.vximm1q_user_ready := vu.io.vec_ximm1q_user_ready
ctrl.io.vec_iface.vximm2q_user_ready := vu.io.vec_ximm2q_user_ready
change how fence.*.cv works, now control processor stalls on the fence instruction
2012-03-09 08:31:57 +01:00
// fences
ctrl.io.vec_iface.vfence_ready := vu.io.vec_fence_ready
hwacha integration: now it compiles correctly!
2012-02-15 08:34:57 +01:00
add vector irq handler
2012-03-14 22:15:28 +01:00
// irqs
ctrl.io.vec_iface.irq := vu.io.irq
ctrl.io.vec_iface.irq_cause := vu.io.irq_cause
dpath.io.vec_iface.irq_aux := vu.io.irq_aux
add vector exception infrastructure
2012-02-26 01:37:56 +01:00
// exceptions
major refactoring on vector exception interface
2012-03-09 10:09:22 +01:00
vu.io.xcpt.exception := ctrl.io.vec_iface.exception
refactored vector exception handling interface
2012-03-14 07:45:10 +01:00
vu.io.xcpt.evac := ctrl.io.vec_iface.evac
vu.io.xcpt.evac_addr := dpath.io.vec_iface.evac_addr.toUFix
vu.io.xcpt.kill := ctrl.io.vec_iface.kill
vu.io.xcpt.hold := ctrl.io.vec_iface.hold
add vector exception infrastructure
2012-02-26 01:37:56 +01:00
refactor vector control logic & datapath in the rocket core
2012-02-15 22:30:22 +01:00
// hooking up vector memory interface
upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache
2012-02-27 08:46:51 +01:00
val storegen = new StoreDataGen
storegen.io.typ := vu.io.dmem_req.bits.typ
storegen.io.din := vu.io.dmem_req.bits.data
Refactored cpu/cache interface to use nested bundles
2012-05-02 03:23:04 +02:00
arb.io.requestor(DMEM_VU).req.valid := vu.io.dmem_req.valid
arb.io.requestor(DMEM_VU).req.bits.kill := vu.io.dmem_req.bits.kill
arb.io.requestor(DMEM_VU).req.bits.cmd := vu.io.dmem_req.bits.cmd
arb.io.requestor(DMEM_VU).req.bits.typ := vu.io.dmem_req.bits.typ
arb.io.requestor(DMEM_VU).req.bits.idx := vu.io.dmem_req.bits.idx
arb.io.requestor(DMEM_VU).req.bits.ppn := Reg(vu.io.dmem_req.bits.ppn)
arb.io.requestor(DMEM_VU).req.bits.data := Reg(storegen.io.dout)
arb.io.requestor(DMEM_VU).req.bits.tag := vu.io.dmem_req.bits.tag
vu.io.dmem_req.ready := arb.io.requestor(DMEM_VU).req.ready
vu.io.dmem_resp.valid := Reg(arb.io.requestor(DMEM_VU).resp.valid)
vu.io.dmem_resp.bits.nack := arb.io.requestor(DMEM_VU).resp.bits.nack
vu.io.dmem_resp.bits.data := arb.io.requestor(DMEM_VU).resp.bits.data_subword
vu.io.dmem_resp.bits.tag := Reg(arb.io.requestor(DMEM_VU).resp.bits.tag)
vu.io.dmem_resp.bits.typ := Reg(arb.io.requestor(DMEM_VU).resp.bits.typ)
expose FMA ports outside of FPU (for the VU)
2012-02-24 02:39:34 +01:00
clean up mul/div interface; use VU mul if HAVE_VEC
2012-02-25 04:22:35 +01:00
// share vector integer multiplier with rocket
dpath.io.vec_imul_req <> vu.io.cp_imul_req
dpath.io.vec_imul_resp <> vu.io.cp_imul_resp
upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache
2012-02-27 08:46:51 +01:00
// share sfma and dfma pipelines with rocket
now vu steals cycles from the fpu's fma alu
2012-02-26 10:54:42 +01:00
fpu.io.sfma <> vu.io.cp_sfma
fpu.io.dfma <> vu.io.cp_dfma
expose FMA ports outside of FPU (for the VU)
2012-02-24 02:39:34 +01:00
}
else
{
Refactored cpu/cache interface to use nested bundles
2012-05-02 03:23:04 +02:00
arb.io.requestor(DMEM_VU).req.valid := Bool(false)
expose FMA ports outside of FPU (for the VU)
2012-02-24 02:39:34 +01:00
if (HAVE_FPU)
{
fpu.io.sfma.valid := Bool(false)
fpu.io.dfma.valid := Bool(false)
}
initial vu integration
2012-02-09 06:43:45 +01:00
}
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
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