riscv/rocket-chip
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rocket-chip/rocket/src/main/scala/ctrl.scala

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change package name and sbt project name to rocket
2012-02-26 02:09:26 +01:00
package rocket
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
import Chisel._
constants as traits
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import Node._
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
import Constants._
import Instructions._
initial vu integration
2012-02-09 06:43:45 +01:00
import hwacha._
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
import ALU._
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
class ioCtrlDpath extends Bundle()
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
{
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
// outputs to datapath
INPUT/OUTPUT orderring swapped
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val sel_pc = UFix(OUTPUT, 3);
new chisel version jar and find and replace INPUT and OUTPUT
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val killd = Bool(OUTPUT);
val ren2 = Bool(OUTPUT);
val ren1 = Bool(OUTPUT);
INPUT/OUTPUT orderring swapped
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val sel_alu2 = UFix(OUTPUT, 3);
new chisel version jar and find and replace INPUT and OUTPUT
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val fn_dw = Bool(OUTPUT);
INPUT/OUTPUT orderring swapped
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val fn_alu = UFix(OUTPUT, 4);
new chisel version jar and find and replace INPUT and OUTPUT
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val mul_val = Bool(OUTPUT);
aggressively clock gate int and fp datapaths
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val mul_fn = Bits(OUTPUT, 2);
merge I$, ITLB, BTB into Frontend
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val mul_kill = Bool(OUTPUT)
new chisel version jar and find and replace INPUT and OUTPUT
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val div_val = Bool(OUTPUT);
aggressively clock gate int and fp datapaths
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val div_fn = Bits(OUTPUT, 2);
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
val div_kill = Bool(OUTPUT)
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 19:28:48 +01:00
val sel_wa = Bool(OUTPUT);
INPUT/OUTPUT orderring swapped
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val sel_wb = UFix(OUTPUT, 3);
val pcr = UFix(OUTPUT, 3)
new chisel version jar and find and replace INPUT and OUTPUT
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val wb_eret = Bool(OUTPUT);
val mem_load = Bool(OUTPUT);
add fp loads/stores
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val ex_fp_val= Bool(OUTPUT);
WIP on FPU
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val mem_fp_val= Bool(OUTPUT);
add fp loads/stores
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val ex_wen = Bool(OUTPUT);
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
val ex_jalr = Bool(OUTPUT)
add fp loads/stores
2012-02-08 08:54:25 +01:00
val mem_wen = Bool(OUTPUT);
val wb_wen = Bool(OUTPUT);
move datapath control signals into control unit because that's where control signals go
2012-02-23 23:43:49 +01:00
val wb_valid = Bool(OUTPUT)
make BTB fully associative; don't use it for JALR JALR created a long path from the ALU in execute stage to an address comparator to the next-PC mux. the benfit was close to nil, anyway.
2012-02-09 10:32:52 +01:00
val flush_inst = Bool(OUTPUT);
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
val ex_mem_type = Bits(OUTPUT, 3)
access faults now write badvaddr PCR register with faulting address
2011-11-10 11:46:09 +01:00
// exception handling
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 19:28:48 +01:00
val exception = Bool(OUTPUT);
INPUT/OUTPUT orderring swapped
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val cause = UFix(OUTPUT, 6);
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 19:28:48 +01:00
val badvaddr_wen = Bool(OUTPUT); // high for a load/store access fault
add vector irq handler
2012-03-14 22:15:28 +01:00
val vec_irq_aux_wen = Bool(OUTPUT)
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
// inputs from datapath
INPUT/OUTPUT orderring swapped
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val inst = Bits(INPUT, 32);
use BTB for JALR
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val jalr_eq = Bool(INPUT)
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 19:28:48 +01:00
val br_eq = Bool(INPUT);
val br_lt = Bool(INPUT);
val br_ltu = Bool(INPUT);
val div_rdy = Bool(INPUT);
val div_result_val = Bool(INPUT);
val mul_rdy = Bool(INPUT);
val mul_result_val = Bool(INPUT);
add fp loads/stores
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val mem_wb = Bool(INPUT);
INPUT/OUTPUT orderring swapped
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val ex_waddr = UFix(INPUT, 5); // write addr from execute stage
val mem_waddr = UFix(INPUT, 5); // write addr from memory stage
val wb_waddr = UFix(INPUT, 5); // write addr from writeback stage
val status = Bits(INPUT, 32);
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 19:28:48 +01:00
val sboard_clr = Bool(INPUT);
INPUT/OUTPUT orderring swapped
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val sboard_clra = UFix(INPUT, 5);
add fp loads/stores
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val fp_sboard_clr = Bool(INPUT);
INPUT/OUTPUT orderring swapped
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val fp_sboard_clra = UFix(INPUT, 5);
val fp_sboard_wb_waddr = UFix(INPUT, 5);
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 19:28:48 +01:00
val irq_timer = Bool(INPUT);
val irq_ipi = Bool(INPUT);
allow back pressure on IPI requests
2012-07-18 07:52:53 +02:00
val pcr_replay = Bool(INPUT)
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
factor out more global constants
2012-11-06 08:52:32 +01:00
abstract trait DecodeConstants
change how fence.*.cv works, now control processor stalls on the fence instruction
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{
val xpr64 = Y;
val decode_default =
Merged consts-as-traits
2012-10-17 01:32:35 +02:00
// jalr eret
// fp_val | renx2 div_val | syscall
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
// | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged
// val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| mul_fn | | s_wa s_wb | sync | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | |
List(N, X,X,BR_X, X,X,X,A2_X, DW_X, FN_X, N,M_X, MT_X, X,MUL_X, X,X,WA_X, WB_X, PCR_X,SYNC_X,X,X,X,X)
decode constant object split into multiple objects
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val table: Array[(Bits, List[Bits])]
}
factor out more global constants
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object XDecode extends DecodeConstants
decode constant object split into multiple objects
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{
val table = Array(
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
// jalr eret
// fp_val | renx2 div_val | syscall
// | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged
// val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| mul_fn | | s_wa s_wb | sync | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | |
BNE-> List(Y, N,N,BR_NE, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N),
BEQ-> List(Y, N,N,BR_EQ, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N),
BLT-> List(Y, N,N,BR_LT, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N),
BLTU-> List(Y, N,N,BR_LTU,N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N),
BGE-> List(Y, N,N,BR_GE, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N),
BGEU-> List(Y, N,N,BR_GEU,N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N),
J-> List(Y, N,N,BR_J, N,N,N,A2_JTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N),
JAL-> List(Y, N,N,BR_J, N,N,N,A2_JTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RA,WB_PC, PCR_N,SYNC_N,N,N,N,N),
JALR_C-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_PC, PCR_N,SYNC_N,N,N,N,N),
JALR_J-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_PC, PCR_N,SYNC_N,N,N,N,N),
JALR_R-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_PC, PCR_N,SYNC_N,N,N,N,N),
RDNPC-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_PC, PCR_N,SYNC_N,N,N,N,N),
LB-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
LH-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
LW-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
LD-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
LBU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
LHU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
LWU-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SB-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SH-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SW-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SD-> List(xpr64,N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOADD_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOSWAP_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOAND_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOMIN_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOMINU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOMAX_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOMAXU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOADD_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOSWAP_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOAND_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOMIN_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOMINU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOMAX_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
AMOMAXU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
LUI-> List(Y, N,N,BR_N, N,N,N,A2_LTYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
ADDI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SLTI -> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SLT, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SLTIU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SLTU,N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
ANDI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_AND, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
ORI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_OR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
XORI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_XOR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SLLI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SL, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SRLI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SRAI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SRA, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
ADD-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SUB-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SUB, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SLT-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SLT, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SLTU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SLTU,N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
riscvAND-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_AND, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
riscvOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_OR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
riscvXOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_XOR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SLL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SL, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SRL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SRA-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SRA, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
ADDIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SLLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SL, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SRLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SRAIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SRA, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
ADDW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SUBW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SUB, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SLLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SL, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SRLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SRAW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SRA, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
MUL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_LO, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
MULH-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_H, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
MULHU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_HU, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
MULHSU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_HSU,N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
MULW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, Y,MUL_LO, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
DIV-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_D, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
DIVU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_DU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
REM-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_R, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
REMU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_RU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
DIVW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_D, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
DIVUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_DU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
REMW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_R, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
REMUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_RU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
SYSCALL-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,Y,N,N),
SETPCR-> List(Y, N,N,BR_N, N,N,N,A2_ITYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_S,SYNC_N,N,N,Y,Y),
CLEARPCR-> List(Y, N,N,BR_N, N,N,N,A2_ITYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_C,SYNC_N,N,N,Y,Y),
ERET-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,Y,N,Y,N),
FENCE-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FENCE, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_D,N,N,N,N),
FENCE_I-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FLA, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_I,N,N,N,Y),
CFLUSH-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FLA, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,Y,Y),
MFPCR-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_F,SYNC_N,N,N,Y,Y),
MTPCR-> List(Y, N,N,BR_N, N,Y,N,A2_RTYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_T,SYNC_N,N,N,Y,Y),
RDTIME-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_TSC,PCR_N,SYNC_N,N,N,N,N),
RDCYCLE-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_TSC,PCR_N,SYNC_N,N,N,N,N),
RDINSTRET-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_IRT,PCR_N,SYNC_N,N,N,N,N))
decode constant object split into multiple objects
2012-10-06 00:50:42 +02:00
}
factor out more global constants
2012-11-06 08:52:32 +01:00
object FDecode extends DecodeConstants
decode constant object split into multiple objects
2012-10-06 00:50:42 +02:00
{
val table = Array(
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
// jalr eret
// fp_val | renx2 div_val | syscall
// | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged
// val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| mul_fn | | s_wa s_wb | sync | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | |
FCVT_S_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_D_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FSGNJ_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FSGNJ_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FSGNJX_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FSGNJX_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FSGNJN_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FSGNJN_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FMIN_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FMIN_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FMAX_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FMAX_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FADD_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FADD_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FSUB_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FSUB_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FMUL_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FMUL_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FMADD_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FMADD_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FMSUB_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FMSUB_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FNMADD_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FNMADD_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FNMSUB_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FNMSUB_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
MFTX_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
MFTX_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_W_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_W_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_WU_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_WU_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_L_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_L_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_LU_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_LU_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FEQ_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FEQ_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FLT_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FLT_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FLE_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FLE_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
MXTF_S-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
MXTF_D-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_S_W-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_D_W-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_S_WU-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_D_WU-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_S_L-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_D_L-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_S_LU-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FCVT_D_LU-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
MFFSR-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
MTFSR-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FLW-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
FLD-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
FSW-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N),
FSD-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N))
decode constant object split into multiple objects
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}
change how fence.*.cv works, now control processor stalls on the fence instruction
2012-03-09 08:31:57 +01:00
factor out more global constants
2012-11-06 08:52:32 +01:00
object VDecode extends DecodeConstants
decode constant object split into multiple objects
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{
val table = Array(
merge I$, ITLB, BTB into Frontend
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// jalr eret
// fp_val | renx2 div_val | syscall
// | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged
// val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| mul_fn | | s_wa s_wb | sync | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | |
VVCFGIVL-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,Y),
VVCFG-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,Y),
VSETVL-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,Y),
VF-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VMVV-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
VMSV-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VFMVV-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
FENCE_V_L-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N),
FENCE_V_G-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_D,N,N,N,N),
VLD-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VLW-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VLWU-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VLH-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VLHU-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VLB-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VLBU-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VSD-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VSW-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VSH-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VSB-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VFLD-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VFLW-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VFSD-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VFSW-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VLSTD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VLSTW-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VLSTWU-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VLSTH-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VLSTHU-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VLSTB-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VLSTBU-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VSSTD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VSSTW-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VSSTH-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VSSTB-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VFLSTD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VFLSTW-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VFSSTD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VFSSTW-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
VENQCMD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,Y,N),
VENQIMM1-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,Y,N),
VENQIMM2-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,Y,N),
VENQCNT-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,Y,N),
VXCPTEVAC-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,Y,N),
VXCPTKILL-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,Y,N),
VXCPTHOLD-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,Y,N))
change how fence.*.cv works, now control processor stalls on the fence instruction
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}
factor out more global constants
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class Control(implicit conf: RocketConfiguration) extends Component
initial commit of rocket chisel project, riscv assembly tests and benchmarks
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{
factor out more global constants
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val io = new Bundle {
val dpath = new ioCtrlDpath
val imem = new IOCPUFrontend()(conf.icache)
val dmem = new ioHellaCache()(conf.dcache)
val dtlb_val = Bool(OUTPUT)
val dtlb_kill = Bool(OUTPUT)
val dtlb_rdy = Bool(INPUT)
val dtlb_miss = Bool(INPUT)
val xcpt_dtlb_ld = Bool(INPUT)
val xcpt_dtlb_st = Bool(INPUT)
val fpu = new ioCtrlFPU
val vec_dpath = new ioCtrlDpathVec
val vec_iface = new ioCtrlVecInterface
}
add fp loads/stores
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factor out more global constants
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var decode_table = XDecode.table
if (HAVE_FPU) decode_table ++= FDecode.table
if (HAVE_VEC) decode_table ++= VDecode.table
change how fence.*.cv works, now control processor stalls on the fence instruction
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factor out more global constants
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val cs = DecodeLogic(io.dpath.inst, XDecode.decode_default, decode_table)
initial vu integration
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merge I$, ITLB, BTB into Frontend
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val id_int_val :: id_fp_val :: id_vec_val :: id_br_type :: id_jalr :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: cs0 = cs
val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_wen :: id_sel_wa :: id_sel_wb :: cs1 = cs0
fence on vvcfg; implement fence.v.g correctly
2012-03-27 23:48:30 +02:00
val id_pcr :: id_sync :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = cs1
initial vu integration
2012-02-09 06:43:45 +01:00
add fp loads/stores
2012-02-08 08:54:25 +01:00
val id_raddr3 = io.dpath.inst(16,12);
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
val id_raddr2 = io.dpath.inst(21,17);
val id_raddr1 = io.dpath.inst(26,22);
fix WAW hazard handling
2012-01-02 09:25:11 +01:00
val id_waddr = Mux(id_sel_wa === WA_RA, RA, io.dpath.inst(31,27));
merge I$, ITLB, BTB into Frontend
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val id_load_use = Bool();
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
aggressively clock gate int and fp datapaths
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val ex_reg_xcpt_interrupt = Reg(resetVal = Bool(false))
val ex_reg_valid = Reg(resetVal = Bool(false))
val ex_reg_eret = Reg(resetVal = Bool(false))
val ex_reg_wen = Reg(resetVal = Bool(false))
val ex_reg_fp_wen = Reg(resetVal = Bool(false))
val ex_reg_flush_inst = Reg(resetVal = Bool(false))
val ex_reg_jalr = Reg(resetVal = Bool(false))
val ex_reg_btb_hit = Reg(resetVal = Bool(false))
val ex_reg_div_val = Reg(resetVal = Bool(false))
val ex_reg_mul_val = Reg(resetVal = Bool(false))
val ex_reg_mem_val = Reg(resetVal = Bool(false))
val ex_reg_xcpt = Reg(resetVal = Bool(false))
val ex_reg_fp_val = Reg(resetVal = Bool(false))
val ex_reg_vec_val = Reg(resetVal = Bool(false))
val ex_reg_replay_next = Reg(resetVal = Bool(false))
val ex_reg_load_use = Reg(resetVal = Bool(false))
val ex_reg_pcr = Reg(resetVal = PCR_N)
val ex_reg_br_type = Reg(resetVal = BR_N)
val ex_reg_mul_fn = Reg(){Bits()}
val ex_reg_mem_cmd = Reg(){Bits()}
val ex_reg_mem_type = Reg(){Bits()}
can now take interrupts on stalled instructions
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val ex_reg_cause = Reg(){UFix()}
aggressively clock gate int and fp datapaths
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val mem_reg_xcpt_interrupt = Reg(resetVal = Bool(false))
val mem_reg_valid = Reg(resetVal = Bool(false))
val mem_reg_eret = Reg(resetVal = Bool(false))
val mem_reg_wen = Reg(resetVal = Bool(false))
val mem_reg_fp_wen = Reg(resetVal = Bool(false))
val mem_reg_flush_inst = Reg(resetVal = Bool(false))
val mem_reg_div_val = Reg(resetVal = Bool(false))
val mem_reg_mul_val = Reg(resetVal = Bool(false))
val mem_reg_mem_val = Reg(resetVal = Bool(false))
val mem_reg_xcpt = Reg(resetVal = Bool(false))
val mem_reg_fp_val = Reg(resetVal = Bool(false))
val mem_reg_replay = Reg(resetVal = Bool(false))
val mem_reg_replay_next = Reg(resetVal = Bool(false))
val mem_reg_pcr = Reg(resetVal = PCR_N)
can now take interrupts on stalled instructions
2012-03-19 09:02:06 +01:00
val mem_reg_cause = Reg(){UFix()}
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
val mem_reg_mem_type = Reg(){Bits()}
val wb_reg_valid = Reg(resetVal = Bool(false))
val wb_reg_pcr = Reg(resetVal = PCR_N)
val wb_reg_wen = Reg(resetVal = Bool(false))
val wb_reg_fp_wen = Reg(resetVal = Bool(false))
val wb_reg_flush_inst = Reg(resetVal = Bool(false))
val wb_reg_eret = Reg(resetVal = Bool(false))
val wb_reg_xcpt = Reg(resetVal = Bool(false))
val wb_reg_replay = Reg(resetVal = Bool(false))
val wb_reg_replay_next = Reg(resetVal = Bool(false))
val wb_reg_cause = Reg(){UFix()}
val wb_reg_fp_val = Reg(resetVal = Bool(false))
val wb_reg_dcache_miss = Reg(io.dmem.resp.bits.miss || io.dmem.resp.bits.nack, resetVal = Bool(false))
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
val wb_reg_div_mul_val = Reg(resetVal = Bool(false))
move PCR writes to WB stage
2012-01-03 00:42:39 +01:00
removing wires
2012-05-24 19:33:15 +02:00
val take_pc = Bool()
val take_pc_wb = Bool()
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
val ctrl_killd = Bool()
val ctrl_killx = Bool()
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
val ctrl_killm = Bool()
can now take interrupts on stalled instructions
2012-03-19 09:02:06 +01:00
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
val id_maskable_interrupts = List(
(io.dpath.irq_ipi, IRQ_IPI),
(io.dpath.irq_timer, IRQ_TIMER))
var id_interrupts = id_maskable_interrupts.map(i => (io.dpath.status(SR_IM+i._2) && i._1, UFix(CAUSE_INTERRUPT+i._2)))
can now take interrupts on stalled instructions
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var vec_replay = Bool(false)
var vec_stalld = Bool(false)
if (HAVE_VEC)
{
// vector control
val vec = new rocketCtrlVec()
io.vec_dpath <> vec.io.dpath
io.vec_iface <> vec.io.iface
fix irt counter bug regarding vector stuff
2012-03-21 01:09:54 +01:00
vec.io.valid := wb_reg_valid
can now take interrupts on stalled instructions
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vec.io.s := io.dpath.status(SR_S)
vec.io.sr_ev := io.dpath.status(SR_EV)
aggressively clock gate int and fp datapaths
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vec.io.exception := wb_reg_xcpt
can now take interrupts on stalled instructions
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vec.io.eret := wb_reg_eret
get rid of vxcptwait
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val vec_dec = new rocketCtrlVecDecoder()
vec_dec.io.inst := io.dpath.inst
val s = io.dpath.status(SR_S)
val mask_cmdq_ready = !vec_dec.io.sigs.enq_cmdq || s && io.vec_iface.vcmdq_ready || !s && io.vec_iface.vcmdq_user_ready
val mask_ximm1q_ready = !vec_dec.io.sigs.enq_ximm1q || s && io.vec_iface.vximm1q_ready || !s && io.vec_iface.vximm1q_user_ready
val mask_ximm2q_ready = !vec_dec.io.sigs.enq_ximm2q || s && io.vec_iface.vximm2q_ready || !s && io.vec_iface.vximm2q_user_ready
val mask_cntq_ready = !vec_dec.io.sigs.enq_cntq || io.vec_iface.vcntq_ready
val mask_pfcmdq_ready = !vec_dec.io.sigs.enq_pfcmdq || io.vec_iface.vpfcmdq_ready
val mask_pfximm1q_ready = !vec_dec.io.sigs.enq_pfximm1q || io.vec_iface.vpfximm1q_ready
val mask_pfximm2q_ready = !vec_dec.io.sigs.enq_pfximm2q || io.vec_iface.vpfximm2q_ready
val mask_pfcntq_ready = !vec_dec.io.sigs.enq_pfcntq || io.vec_iface.vpfcntq_ready
vec_stalld =
improved instruction decoding it now makes use of don't-cares by performing logic minimization
2012-05-02 05:16:36 +02:00
id_vec_val && (
get rid of vxcptwait
2012-03-21 23:08:48 +01:00
!mask_cmdq_ready || !mask_ximm1q_ready || !mask_ximm2q_ready || !mask_cntq_ready ||
improved instruction decoding it now makes use of don't-cares by performing logic minimization
2012-05-02 05:16:36 +02:00
!mask_pfcmdq_ready || !mask_pfximm1q_ready || !mask_pfximm2q_ready || !mask_pfcntq_ready ||
vec_dec.io.sigs.vfence && !vec.io.vfence_ready)
get rid of vxcptwait
2012-03-21 23:08:48 +01:00
can now take interrupts on stalled instructions
2012-03-19 09:02:06 +01:00
vec_replay = vec.io.replay
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
id_interrupts = id_interrupts :+ (vec.io.irq, vec.io.irq_cause)
can now take interrupts on stalled instructions
2012-03-19 09:02:06 +01:00
}
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
val (id_interrupt_unmasked, id_interrupt_cause) = checkExceptions(id_interrupts)
val id_interrupt = io.dpath.status(SR_ET) && id_interrupt_unmasked
def checkExceptions(x: Seq[(Bits, UFix)]) =
(x.map(_._1).reduce(_||_), PriorityMux(x))
improved instruction decoding it now makes use of don't-cares by performing logic minimization
2012-05-02 05:16:36 +02:00
// executing ERET when traps are enabled causes an illegal instruction exception
val illegal_inst = !id_int_val.toBool || (id_eret.toBool && io.dpath.status(SR_ET))
can now take interrupts on stalled instructions
2012-03-19 09:02:06 +01:00
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
val (id_xcpt, id_cause) = checkExceptions(List(
(id_interrupt, id_interrupt_cause),
(io.imem.resp.bits.xcpt_ma, UFix(0)),
(io.imem.resp.bits.xcpt_if, UFix(1)),
(illegal_inst, UFix(2)),
(id_privileged && !io.dpath.status(SR_S), UFix(3)),
(id_fp_val && !io.dpath.status(SR_EF), UFix(4)),
(id_syscall, UFix(6)),
(id_vec_val && !io.dpath.status(SR_EV), UFix(12))))
ex_reg_xcpt_interrupt := id_interrupt && !take_pc && io.imem.resp.valid
when (id_xcpt) { ex_reg_cause := id_cause }
when (ctrl_killd) {
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
ex_reg_jalr := Bool(false)
update to new chisel
2012-02-12 02:20:33 +01:00
ex_reg_btb_hit := Bool(false);
ex_reg_div_val := Bool(false);
ex_reg_mul_val := Bool(false);
ex_reg_mem_val := Bool(false);
move datapath control signals into control unit because that's where control signals go
2012-02-23 23:43:49 +01:00
ex_reg_valid := Bool(false);
update to new chisel
2012-02-12 02:20:33 +01:00
ex_reg_wen := Bool(false);
ex_reg_fp_wen := Bool(false);
ex_reg_eret := Bool(false);
ex_reg_flush_inst := Bool(false);
ex_reg_fp_val := Bool(false);
ex_reg_vec_val := Bool(false);
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
ex_reg_replay_next := Bool(false);
update to new chisel
2012-02-12 02:20:33 +01:00
ex_reg_load_use := Bool(false);
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
ex_reg_pcr := PCR_N
ex_reg_br_type := BR_N
ex_reg_xcpt := Bool(false)
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
update to new chisel
2012-02-12 02:20:33 +01:00
.otherwise {
ex_reg_br_type := id_br_type;
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
ex_reg_jalr := id_jalr
ex_reg_btb_hit := io.imem.resp.bits.taken
move rd=0 check into bypass logic before, the check was in the write enable logic, but moving it obviated an awkward corner case for mtpcr with rd=0.
2012-11-05 10:30:57 +01:00
ex_reg_div_val := id_div_val
ex_reg_mul_val := id_mul_val
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
ex_reg_mul_fn := id_mul_fn.toUFix
update to new chisel
2012-02-12 02:20:33 +01:00
ex_reg_mem_val := id_mem_val.toBool;
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
ex_reg_valid := Bool(true)
new supervisor mode
2012-03-24 21:03:31 +01:00
ex_reg_pcr := id_pcr
move rd=0 check into bypass logic before, the check was in the write enable logic, but moving it obviated an awkward corner case for mtpcr with rd=0.
2012-11-05 10:30:57 +01:00
ex_reg_wen := id_wen
improved instruction decoding it now makes use of don't-cares by performing logic minimization
2012-05-02 05:16:36 +02:00
ex_reg_fp_wen := id_fp_val && io.fpu.dec.wen
update to new chisel
2012-02-12 02:20:33 +01:00
ex_reg_eret := id_eret.toBool;
ex_reg_flush_inst := (id_sync === SYNC_I);
improved instruction decoding it now makes use of don't-cares by performing logic minimization
2012-05-02 05:16:36 +02:00
ex_reg_fp_val := id_fp_val
update to new chisel
2012-02-12 02:20:33 +01:00
ex_reg_vec_val := id_vec_val.toBool
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
ex_reg_replay_next := id_replay_next
update to new chisel
2012-02-12 02:20:33 +01:00
ex_reg_load_use := id_load_use;
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
ex_reg_mem_cmd := id_mem_cmd
ex_reg_mem_type := id_mem_type.toUFix
ex_reg_xcpt := id_xcpt
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
fix (?) external memory request nack interface
2012-02-24 10:42:33 +01:00
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
val br_taken =
Mux(ex_reg_br_type === BR_EQ, io.dpath.br_eq,
Mux(ex_reg_br_type === BR_NE, ~io.dpath.br_eq,
Mux(ex_reg_br_type === BR_LT, io.dpath.br_lt,
Mux(ex_reg_br_type === BR_GE, ~io.dpath.br_lt,
Mux(ex_reg_br_type === BR_LTU, io.dpath.br_ltu,
Mux(ex_reg_br_type === BR_GEU, ~io.dpath.br_ltu,
ex_reg_br_type === BR_J))))))
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
val take_pc_ex = !Mux(ex_reg_jalr, ex_reg_btb_hit && io.dpath.jalr_eq, ex_reg_btb_hit === br_taken)
val (ex_xcpt, ex_cause) = checkExceptions(List(
(ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause),
(ex_reg_fp_val && io.fpu.illegal_rm, UFix(2))))
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb
when (ex_xcpt) { mem_reg_cause := ex_cause }
mem_reg_div_val := ex_reg_div_val && io.dpath.div_rdy
mem_reg_mul_val := ex_reg_mul_val && io.dpath.mul_rdy
when (ctrl_killx) {
move datapath control signals into control unit because that's where control signals go
2012-02-23 23:43:49 +01:00
mem_reg_valid := Bool(false);
new supervisor mode
2012-03-24 21:03:31 +01:00
mem_reg_pcr := PCR_N
update to new chisel
2012-02-12 02:20:33 +01:00
mem_reg_wen := Bool(false);
mem_reg_fp_wen := Bool(false);
mem_reg_eret := Bool(false);
mem_reg_mem_val := Bool(false);
mem_reg_flush_inst := Bool(false);
WIP on FPU
2012-02-12 13:36:01 +01:00
mem_reg_fp_val := Bool(false);
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
mem_reg_replay_next := Bool(false)
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
mem_reg_xcpt := Bool(false)
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
}
update to new chisel
2012-02-12 02:20:33 +01:00
.otherwise {
move datapath control signals into control unit because that's where control signals go
2012-02-23 23:43:49 +01:00
mem_reg_valid := ex_reg_valid
new supervisor mode
2012-03-24 21:03:31 +01:00
mem_reg_pcr := ex_reg_pcr
update to new chisel
2012-02-12 02:20:33 +01:00
mem_reg_wen := ex_reg_wen;
mem_reg_fp_wen := ex_reg_fp_wen;
mem_reg_eret := ex_reg_eret;
mem_reg_mem_val := ex_reg_mem_val;
mem_reg_flush_inst := ex_reg_flush_inst;
WIP on FPU
2012-02-12 13:36:01 +01:00
mem_reg_fp_val := ex_reg_fp_val
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
mem_reg_replay_next := ex_reg_replay_next
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
mem_reg_mem_type := ex_reg_mem_type
mem_reg_xcpt := ex_xcpt
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
}
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
val (mem_xcpt, mem_cause) = checkExceptions(List(
(mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
(mem_reg_mem_val && io.dmem.xcpt.ma.ld, UFix( 8)),
(mem_reg_mem_val && io.dmem.xcpt.ma.st, UFix( 9)),
(mem_reg_mem_val && io.xcpt_dtlb_ld, UFix(10)),
(mem_reg_mem_val && io.xcpt_dtlb_st, UFix(11))))
wb_reg_xcpt := mem_xcpt && !take_pc_wb && !wb_reg_replay_next
when (mem_xcpt) { wb_reg_cause := mem_cause }
move PCR writes to WB stage
2012-01-03 00:42:39 +01:00
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
when (ctrl_killm) {
move datapath control signals into control unit because that's where control signals go
2012-02-23 23:43:49 +01:00
wb_reg_valid := Bool(false)
new supervisor mode
2012-03-24 21:03:31 +01:00
wb_reg_pcr := PCR_N
update to new chisel
2012-02-12 02:20:33 +01:00
wb_reg_wen := Bool(false);
wb_reg_fp_wen := Bool(false);
wb_reg_eret := Bool(false);
wb_reg_flush_inst := Bool(false);
wb_reg_div_mul_val := Bool(false);
add FP ops mftx, mxtf, mtfsr, mffsr
2012-02-13 05:12:53 +01:00
wb_reg_fp_val := Bool(false)
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
wb_reg_replay_next := Bool(false)
move PCR writes to WB stage
2012-01-03 00:42:39 +01:00
}
update to new chisel
2012-02-12 02:20:33 +01:00
.otherwise {
move datapath control signals into control unit because that's where control signals go
2012-02-23 23:43:49 +01:00
wb_reg_valid := mem_reg_valid
new supervisor mode
2012-03-24 21:03:31 +01:00
wb_reg_pcr := mem_reg_pcr
update to new chisel
2012-02-12 02:20:33 +01:00
wb_reg_wen := mem_reg_wen;
wb_reg_fp_wen := mem_reg_fp_wen;
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
wb_reg_eret := mem_reg_eret && !mem_reg_replay
update to new chisel
2012-02-12 02:20:33 +01:00
wb_reg_flush_inst := mem_reg_flush_inst;
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
wb_reg_div_mul_val := mem_reg_div_val || mem_reg_mul_val
add FP ops mftx, mxtf, mtfsr, mffsr
2012-02-13 05:12:53 +01:00
wb_reg_fp_val := mem_reg_fp_val
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
wb_reg_replay_next := mem_reg_replay_next
move PCR writes to WB stage
2012-01-03 00:42:39 +01:00
}
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
parameterize the scoreboards
2012-02-14 03:12:23 +01:00
val sboard = new rocketCtrlSboard(32, 3, 2);
sboard.io.r(0).addr := id_raddr2.toUFix;
sboard.io.r(1).addr := id_raddr1.toUFix;
sboard.io.r(2).addr := id_waddr.toUFix;
add fp loads/stores
2012-02-08 08:54:25 +01:00
// scoreboard set (for D$ misses, div, mul)
parameterize the scoreboards
2012-02-14 03:12:23 +01:00
sboard.io.w(0).en := wb_reg_div_mul_val || wb_reg_dcache_miss && wb_reg_wen
sboard.io.w(0).data := Bool(true)
sboard.io.w(0).addr := io.dpath.wb_waddr
add fp loads/stores
2012-02-08 08:54:25 +01:00
parameterize the scoreboards
2012-02-14 03:12:23 +01:00
sboard.io.w(1).en := io.dpath.sboard_clr
sboard.io.w(1).data := Bool(false)
sboard.io.w(1).addr := io.dpath.sboard_clra
add fp loads/stores
2012-02-08 08:54:25 +01:00
parameterize the scoreboards
2012-02-14 03:12:23 +01:00
val id_stall_raddr2 = id_renx2.toBool && sboard.io.r(0).data
val id_stall_raddr1 = id_renx1.toBool && sboard.io.r(1).data
val id_stall_waddr = id_wen.toBool && sboard.io.r(2).data
add fp loads/stores
2012-02-08 08:54:25 +01:00
var id_stall_fpu = Bool(false)
if (HAVE_FPU) {
declaring success on FPU for now
2012-02-15 04:11:57 +01:00
val fp_sboard = new rocketCtrlSboard(32, 4, 3);
parameterize the scoreboards
2012-02-14 03:12:23 +01:00
fp_sboard.io.r(0).addr := id_raddr1.toUFix
fp_sboard.io.r(1).addr := id_raddr2.toUFix
fp_sboard.io.r(2).addr := id_raddr3.toUFix
fp_sboard.io.r(3).addr := id_waddr.toUFix
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
fp_sboard.io.w(0).en := wb_reg_dcache_miss && wb_reg_fp_wen || io.fpu.sboard_set
parameterize the scoreboards
2012-02-14 03:12:23 +01:00
fp_sboard.io.w(0).data := Bool(true)
two bug fixes to fpu
2012-04-01 07:23:51 +02:00
fp_sboard.io.w(0).addr := io.dpath.fp_sboard_wb_waddr
parameterize the scoreboards
2012-02-14 03:12:23 +01:00
fp_sboard.io.w(1).en := io.dpath.fp_sboard_clr
fp_sboard.io.w(1).data := Bool(false)
fp_sboard.io.w(1).addr := io.dpath.fp_sboard_clra
declaring success on FPU for now
2012-02-15 04:11:57 +01:00
fp_sboard.io.w(2).en := io.fpu.sboard_clr
fp_sboard.io.w(2).data := Bool(false)
fp_sboard.io.w(2).addr := io.fpu.sboard_clra
parameterize the scoreboards
2012-02-14 03:12:23 +01:00
id_stall_fpu = io.fpu.dec.ren1 && fp_sboard.io.r(0).data ||
io.fpu.dec.ren2 && fp_sboard.io.r(1).data ||
io.fpu.dec.ren3 && fp_sboard.io.r(2).data ||
io.fpu.dec.wen && fp_sboard.io.r(3).data
add fp loads/stores
2012-02-08 08:54:25 +01:00
}
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
// replay inst in ex stage
add fp loads/stores
2012-02-08 08:54:25 +01:00
val replay_ex = wb_reg_dcache_miss && ex_reg_load_use || mem_reg_flush_inst ||
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
ex_reg_mem_val && !(io.dmem.req.ready && io.dtlb_rdy) ||
fix mul/div deadlock bug If independent multiplies or independent divides were issued back-to-back, the second wouldn't execute, causing the register to be busy forever.
2012-01-31 06:14:28 +01:00
ex_reg_div_val && !io.dpath.div_rdy ||
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
ex_reg_mul_val && !io.dpath.mul_rdy ||
mem_reg_replay_next
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
ctrl_killx := take_pc_wb || replay_ex
// replay inst in mem stage
val mem_ll_wb = io.dpath.mem_wb || io.dpath.mul_result_val || io.dpath.div_result_val
val dmem_kill_mem = mem_reg_valid && (io.dtlb_miss || io.dmem.resp.bits.nack)
val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem
val replay_mem = dmem_kill_mem || mem_reg_wen && mem_ll_wb || mem_reg_replay || fpu_kill_mem
val killm_common = mem_reg_wen && mem_ll_wb || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
ctrl_killm := killm_common || mem_xcpt || dmem_kill_mem || fpu_kill_mem
move replays to writeback stage
2012-01-18 06:12:31 +01:00
update to new chisel
2012-02-12 02:20:33 +01:00
mem_reg_replay := replay_ex && !take_pc_wb;
Don't replay from EX stage. EX replays are now handled from MEM. We may move them to WB.
2011-12-10 04:42:58 +01:00
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
wb_reg_replay := replay_mem && !take_pc_wb
fixes to exception and dcache miss/blocked handling
2011-11-02 21:32:32 +01:00
allow back pressure on IPI requests
2012-07-18 07:52:53 +02:00
val replay_wb = wb_reg_replay || vec_replay || io.dpath.pcr_replay
fix vcmdq full replay logic
2012-02-16 02:49:12 +01:00
fix when badvaddr is set
2012-01-31 02:15:42 +01:00
// write cause to PCR on an exception
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
io.dpath.exception := wb_reg_xcpt
io.dpath.cause := wb_reg_cause
io.dpath.badvaddr_wen := wb_reg_xcpt && (wb_reg_cause === UFix(10) || wb_reg_cause === UFix(11))
io.dpath.vec_irq_aux_wen := wb_reg_xcpt && wb_reg_cause >= UFix(24) && wb_reg_cause < UFix(32)
// control transfer from ex/wb
take_pc_wb := wb_reg_replay || vec_replay || wb_reg_xcpt || wb_reg_eret
take_pc := take_pc_ex || take_pc_wb;
fix when badvaddr is set
2012-01-31 02:15:42 +01:00
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
io.dpath.sel_pc :=
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
Mux(wb_reg_xcpt, PC_PCR, // exception
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
Mux(wb_reg_eret, PC_PCR, // eret instruction
Mux(replay_wb, PC_WB, // replay
Mux(ex_reg_jalr, PC_EX, // JALR
Mux(!ex_reg_btb_hit, PC_EX, // mispredicted taken branch
PC_EX4))))) // mispredicted not taken branch
use BTB for JALR
2012-10-12 01:50:15 +02:00
io.imem.req.bits.mispredict := !take_pc_wb && take_pc_ex
io.imem.req.bits.taken := !ex_reg_btb_hit || ex_reg_jalr
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
io.imem.req.valid := take_pc
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
fix WAW hazard handling
2012-01-02 09:25:11 +01:00
// stall for RAW/WAW hazards on loads, AMOs, and mul/div in execute stage.
add fp loads/stores
2012-02-08 08:54:25 +01:00
val data_hazard_ex = ex_reg_wen &&
(id_renx1.toBool && id_raddr1 === io.dpath.ex_waddr ||
id_renx2.toBool && id_raddr2 === io.dpath.ex_waddr ||
id_wen.toBool && id_waddr === io.dpath.ex_waddr)
val fp_data_hazard_ex = ex_reg_fp_wen &&
WIP on FPU
2012-02-12 13:36:01 +01:00
(io.fpu.dec.ren1 && id_raddr1 === io.dpath.ex_waddr ||
io.fpu.dec.ren2 && id_raddr2 === io.dpath.ex_waddr ||
io.fpu.dec.ren3 && id_raddr3 === io.dpath.ex_waddr ||
io.fpu.dec.wen && id_waddr === io.dpath.ex_waddr)
add FP ops mftx, mxtf, mtfsr, mffsr
2012-02-13 05:12:53 +01:00
val id_ex_hazard = data_hazard_ex && (ex_reg_mem_val || ex_reg_div_val || ex_reg_mul_val || ex_reg_fp_val) ||
fp_data_hazard_ex && (ex_reg_mem_val || ex_reg_fp_val)
dcache loads working - 1/2 cycle load/use delay depending on load type
2011-11-02 05:25:52 +01:00
fix WAW hazard handling
2012-01-02 09:25:11 +01:00
// stall for RAW/WAW hazards on LB/LH and mul/div in memory stage.
add fp loads/stores
2012-02-08 08:54:25 +01:00
val mem_mem_cmd_bh =
(mem_reg_mem_type === MT_B) || (mem_reg_mem_type === MT_BU) ||
(mem_reg_mem_type === MT_H) || (mem_reg_mem_type === MT_HU)
val data_hazard_mem = mem_reg_wen &&
move rd=0 check into bypass logic before, the check was in the write enable logic, but moving it obviated an awkward corner case for mtpcr with rd=0.
2012-11-05 10:30:57 +01:00
(id_raddr1 != UFix(0) && id_renx1 && id_raddr1 === io.dpath.mem_waddr ||
id_raddr2 != UFix(0) && id_renx2 && id_raddr2 === io.dpath.mem_waddr ||
id_waddr != UFix(0) && id_wen && id_waddr === io.dpath.mem_waddr)
add fp loads/stores
2012-02-08 08:54:25 +01:00
val fp_data_hazard_mem = mem_reg_fp_wen &&
WIP on FPU
2012-02-12 13:36:01 +01:00
(io.fpu.dec.ren1 && id_raddr1 === io.dpath.mem_waddr ||
io.fpu.dec.ren2 && id_raddr2 === io.dpath.mem_waddr ||
io.fpu.dec.ren3 && id_raddr3 === io.dpath.mem_waddr ||
io.fpu.dec.wen && id_waddr === io.dpath.mem_waddr)
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
val id_mem_hazard = data_hazard_mem && (mem_reg_mem_val && mem_mem_cmd_bh || mem_reg_div_val || mem_reg_mul_val || mem_reg_fp_val) ||
add FP ops mftx, mxtf, mtfsr, mffsr
2012-02-13 05:12:53 +01:00
fp_data_hazard_mem && mem_reg_fp_val
add fp loads/stores
2012-02-08 08:54:25 +01:00
id_load_use := mem_reg_mem_val && (data_hazard_mem || fp_data_hazard_mem)
fix WAW hazard handling
2012-01-02 09:25:11 +01:00
// stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback.
add fp loads/stores
2012-02-08 08:54:25 +01:00
val data_hazard_wb = wb_reg_wen &&
move rd=0 check into bypass logic before, the check was in the write enable logic, but moving it obviated an awkward corner case for mtpcr with rd=0.
2012-11-05 10:30:57 +01:00
(id_raddr1 != UFix(0) && id_renx1 && id_raddr1 === io.dpath.wb_waddr ||
id_raddr2 != UFix(0) && id_renx2 && id_raddr2 === io.dpath.wb_waddr ||
id_waddr != UFix(0) && id_wen && id_waddr === io.dpath.wb_waddr)
add fp loads/stores
2012-02-08 08:54:25 +01:00
val fp_data_hazard_wb = wb_reg_fp_wen &&
WIP on FPU
2012-02-12 13:36:01 +01:00
(io.fpu.dec.ren1 && id_raddr1 === io.dpath.wb_waddr ||
io.fpu.dec.ren2 && id_raddr2 === io.dpath.wb_waddr ||
io.fpu.dec.ren3 && id_raddr3 === io.dpath.wb_waddr ||
io.fpu.dec.wen && id_waddr === io.dpath.wb_waddr)
add fp loads/stores
2012-02-08 08:54:25 +01:00
val id_wb_hazard = data_hazard_wb && (wb_reg_dcache_miss || wb_reg_div_mul_val) ||
add FP ops mftx, mxtf, mtfsr, mffsr
2012-02-13 05:12:53 +01:00
fp_data_hazard_wb && (wb_reg_dcache_miss || wb_reg_fp_val)
fix WAW hazard handling
2012-01-02 09:25:11 +01:00
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
val ctrl_stalld =
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
id_ex_hazard || id_mem_hazard || id_wb_hazard ||
id_stall_raddr1 || id_stall_raddr2 || id_stall_waddr ||
id_fp_val && id_stall_fpu ||
id_mem_val && !(io.dmem.req.ready && io.dtlb_rdy) ||
vec_stalld
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
ctrl_killd := !io.imem.resp.valid || take_pc || ctrl_stalld || id_interrupt
io.dpath.killd := take_pc || ctrl_stalld && !id_interrupt
make BTB fully associative; don't use it for JALR JALR created a long path from the ALU in execute stage to an address comparator to the next-PC mux. the benfit was close to nil, anyway.
2012-02-09 10:32:52 +01:00
io.dpath.flush_inst := wb_reg_flush_inst;
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
io.imem.resp.ready := take_pc || !ctrl_stalld
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
io.imem.req.bits.invalidate := wb_reg_flush_inst
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
add fp loads/stores
2012-02-08 08:54:25 +01:00
io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen
fix WAW hazard handling
2012-01-02 09:25:11 +01:00
io.dpath.ren2 := id_renx2.toBool;
io.dpath.ren1 := id_renx1.toBool;
improved instruction decoding it now makes use of don't-cares by performing logic minimization
2012-05-02 05:16:36 +02:00
io.dpath.sel_alu2 := id_sel_alu2.toUFix
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
io.dpath.fn_dw := id_fn_dw.toBool;
improved instruction decoding it now makes use of don't-cares by performing logic minimization
2012-05-02 05:16:36 +02:00
io.dpath.fn_alu := id_fn_alu.toUFix
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
io.dpath.div_fn := ex_reg_mul_fn
io.dpath.div_val := ex_reg_div_val
io.dpath.div_kill := mem_reg_div_val && killm_common
io.dpath.mul_fn := ex_reg_mul_fn
io.dpath.mul_val := ex_reg_mul_val
io.dpath.mul_kill := mem_reg_mul_val && killm_common
add fp loads/stores
2012-02-08 08:54:25 +01:00
io.dpath.ex_fp_val:= ex_reg_fp_val;
WIP on FPU
2012-02-12 13:36:01 +01:00
io.dpath.mem_fp_val:= mem_reg_fp_val;
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
io.dpath.ex_jalr := ex_reg_jalr
add fp loads/stores
2012-02-08 08:54:25 +01:00
io.dpath.ex_wen := ex_reg_wen;
io.dpath.mem_wen := mem_reg_wen;
io.dpath.wb_wen := wb_reg_wen;
fix irt counter bug regarding vector stuff
2012-03-21 01:09:54 +01:00
io.dpath.wb_valid := wb_reg_valid && !vec_replay
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
io.dpath.sel_wa := id_sel_wa.toBool;
improved instruction decoding it now makes use of don't-cares by performing logic minimization
2012-05-02 05:16:36 +02:00
io.dpath.sel_wb := id_sel_wb.toUFix
new supervisor mode
2012-03-24 21:03:31 +01:00
io.dpath.pcr := wb_reg_pcr.toUFix
move PCR writes to WB stage
2012-01-03 00:42:39 +01:00
io.dpath.wb_eret := wb_reg_eret;
move store data generation into EX stage doing so removes it from the critical path of FP store unrecoding.
2012-02-12 10:35:55 +01:00
io.dpath.ex_mem_type := ex_reg_mem_type
Don't replay from EX stage. EX replays are now handled from MEM. We may move them to WB.
2011-12-10 04:42:58 +01:00
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
io.fpu.valid := !ctrl_killd && id_fp_val
io.fpu.killx := ctrl_killx
merge I$, ITLB, BTB into Frontend
2012-10-10 06:35:03 +02:00
io.fpu.killm := killm_common
WIP on FPU
2012-02-12 13:36:01 +01:00
Refactored cpu/cache interface to use nested bundles
2012-05-02 03:23:04 +02:00
io.dtlb_val := ex_reg_mem_val
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
io.dtlb_kill := !mem_reg_valid
Refactored cpu/cache interface to use nested bundles
2012-05-02 03:23:04 +02:00
io.dmem.req.valid := ex_reg_mem_val
aggressively clock gate int and fp datapaths
2012-11-05 01:40:14 +01:00
io.dmem.req.bits.kill := killm_common || mem_xcpt || io.dtlb_miss
Refactored cpu/cache interface to use nested bundles
2012-05-02 03:23:04 +02:00
io.dmem.req.bits.cmd := ex_reg_mem_cmd
io.dmem.req.bits.typ := ex_reg_mem_type
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
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