riscv/rocket-chip
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rocket-chip/rocket/src/main/scala/ctrl.scala

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initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
package Top {
import Chisel._
import Node._;
import Constants._
import Instructions._
initial vu integration
2012-02-09 06:43:45 +01:00
import hwacha._
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
class ioCtrlDpath extends Bundle()
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
{
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
// outputs to datapath
improve id/ex datapath move operand selection into decode stage; simplify bypassing
2012-02-08 15:47:26 +01:00
val sel_pc = UFix(3, OUTPUT);
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 19:28:48 +01:00
val wen_btb = Bool(OUTPUT);
val clr_btb = Bool(OUTPUT);
val stallf = Bool(OUTPUT);
val stalld = Bool(OUTPUT);
val killf = Bool(OUTPUT);
val killd = Bool(OUTPUT);
val killx = Bool(OUTPUT);
val killm = Bool(OUTPUT);
val ren2 = Bool(OUTPUT);
val ren1 = Bool(OUTPUT);
improve id/ex datapath move operand selection into decode stage; simplify bypassing
2012-02-08 15:47:26 +01:00
val sel_alu2 = UFix(3, OUTPUT);
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 19:28:48 +01:00
val fn_dw = Bool(OUTPUT);
val fn_alu = UFix(4, OUTPUT);
val mul_val = Bool(OUTPUT);
val mul_fn = UFix(2, OUTPUT);
val div_val = Bool(OUTPUT);
val div_fn = UFix(2, OUTPUT);
val sel_wa = Bool(OUTPUT);
val sel_wb = UFix(3, OUTPUT);
val ren_pcr = Bool(OUTPUT);
val wen_pcr = Bool(OUTPUT);
val id_eret = Bool(OUTPUT);
val wb_eret = Bool(OUTPUT);
val mem_load = Bool(OUTPUT);
add external memory request interface for vec unit
2012-02-09 07:30:45 +01:00
val ex_ext_mem_val = Bool(OUTPUT);
add fp loads/stores
2012-02-08 08:54:25 +01:00
val ex_fp_val= Bool(OUTPUT);
val ex_wen = Bool(OUTPUT);
val mem_wen = Bool(OUTPUT);
val wb_wen = Bool(OUTPUT);
added ei and di instructions
2011-11-14 22:48:49 +01:00
// enable/disable interrupts
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 19:28:48 +01:00
val irq_enable = Bool(OUTPUT);
val irq_disable = Bool(OUTPUT);
access faults now write badvaddr PCR register with faulting address
2011-11-10 11:46:09 +01:00
// exception handling
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 19:28:48 +01:00
val exception = Bool(OUTPUT);
val cause = UFix(5,OUTPUT);
val badvaddr_wen = Bool(OUTPUT); // high for a load/store access fault
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
// inputs from datapath
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 19:28:48 +01:00
val xcpt_ma_inst = Bool(INPUT); // high on a misaligned/illegal virtual PC
val btb_hit = Bool(INPUT);
val btb_match = Bool(INPUT);
val inst = Bits(32, INPUT);
val br_eq = Bool(INPUT);
val br_lt = Bool(INPUT);
val br_ltu = Bool(INPUT);
val div_rdy = Bool(INPUT);
val div_result_val = Bool(INPUT);
val mul_rdy = Bool(INPUT);
val mul_result_val = Bool(INPUT);
add fp loads/stores
2012-02-08 08:54:25 +01:00
val mem_wb = Bool(INPUT);
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 19:28:48 +01:00
val ex_waddr = UFix(5,INPUT); // write addr from execute stage
val mem_waddr = UFix(5,INPUT); // write addr from memory stage
val wb_waddr = UFix(5,INPUT); // write addr from writeback stage
val status = Bits(17, INPUT);
val sboard_clr = Bool(INPUT);
val sboard_clra = UFix(5, INPUT);
add fp loads/stores
2012-02-08 08:54:25 +01:00
val fp_sboard_clr = Bool(INPUT);
val fp_sboard_clra = UFix(5, INPUT);
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 19:28:48 +01:00
val mem_valid = Bool(INPUT); // high if there's a valid (not flushed) instruction in mem stage
val irq_timer = Bool(INPUT);
val irq_ipi = Bool(INPUT);
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
class ioCtrlAll extends Bundle()
{
val dpath = new ioCtrlDpath();
fixed console i/o
2011-12-01 07:51:59 +01:00
val console = new ioConsole(List("rdy"));
remove icache req_rdy signal
2012-01-12 03:27:11 +01:00
val imem = new ioImem(List("req_val", "resp_val")).flip();
add fp loads/stores
2012-02-08 08:54:25 +01:00
val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_nack")).flip();
add external memory request interface for vec unit
2012-02-09 07:30:45 +01:00
val ext_mem = new ioDmem(List("req_val", "req_cmd", "req_type", "resp_nack"))
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 19:28:48 +01:00
val dtlb_val = Bool(OUTPUT);
val dtlb_kill = Bool(OUTPUT);
val dtlb_rdy = Bool(INPUT);
val dtlb_miss = Bool(INPUT);
val flush_inst = Bool(OUTPUT);
val xcpt_dtlb_ld = Bool(INPUT);
val xcpt_dtlb_st = Bool(INPUT);
val xcpt_itlb = Bool(INPUT);
val xcpt_ma_ld = Bool(INPUT);
val xcpt_ma_st = Bool(INPUT);
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
class rocketCtrl extends Component
{
val io = new ioCtrlAll();
add fp loads/stores
2012-02-08 08:54:25 +01:00
val fpdec = new rocketFPUDecoder
fpdec.io.inst := io.dpath.inst
more cache fixes, more test harness debug output
2011-11-14 08:32:18 +01:00
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
val xpr64 = Y;
val cs =
ListLookup(io.dpath.inst,
hook up the vector command queue
2012-02-09 10:28:16 +01:00
// eret
// | syscall
// vec_val mem_val mul_val div_val renpcr | | privileged
// val | brtype renx2 renx1 s_alu2 dw alu | mem_cmd mem_type| mul_fn | div_fn wen s_wa s_wb | wenpcr irq sync | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | |
List(N, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),Array(
BNE-> List(Y, N,BR_NE, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
BEQ-> List(Y, N,BR_EQ, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
BLT-> List(Y, N,BR_LT, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
BLTU-> List(Y, N,BR_LTU,REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
BGE-> List(Y, N,BR_GE, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
BGEU-> List(Y, N,BR_GEU,REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
J-> List(Y, N,BR_J, REN_N,REN_N,A2_JTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
JAL-> List(Y, N,BR_J, REN_N,REN_N,A2_JTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RA,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
JALR_C-> List(Y, N,BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
JALR_J-> List(Y, N,BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
JALR_R-> List(Y, N,BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
RDNPC-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
LB-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_B, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
LH-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_H, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
LW-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
LD-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
LBU-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_BU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
LHU-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_HU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
LWU-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_WU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SB-> List(Y, N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_B, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SH-> List(Y, N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_H, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SW-> List(Y, N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SD-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOADD_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOSWAP_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOAND_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOOR_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOMIN_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MIN, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOMINU_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOMAX_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOMAXU_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOADD_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOSWAP_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOAND_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOOR_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOMIN_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MIN, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOMINU_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOMAX_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
AMOMAXU_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
LUI-> List(Y, N,BR_N, REN_N,REN_N,A2_LTYPE,DW_XPR,FN_OP2, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
ADDI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SLTI -> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SLTIU-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SLTU,M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
ANDI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_AND, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
ORI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_OR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
XORI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_XOR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SLLI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SRLI-> List(Y_SH, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SRAI-> List(Y_SH, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
ADD-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SUB-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SUB, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SLT-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SLTU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SLTU,M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
riscvAND-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_AND, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
riscvOR-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_OR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
riscvXOR-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_XOR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SLL-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SRL-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SRA-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
ADDIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SLLIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SRLIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SRAIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
ADDW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SUBW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SUB, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SLLW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SRLW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SRAW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
MUL-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
MULH-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HS, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
MULHU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HU, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
MULHSU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HSU,N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
MULW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
DIV-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_D, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
DIVU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_DU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
REM-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_R, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
REMU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_RU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
DIVW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_D, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
DIVUW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_DU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
REMW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_R, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
REMUW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_RU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
SYSCALL-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,Y,N,N),
EI-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_EI,SYNC_N,N,N,Y,Y),
DI-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_DI,SYNC_N,N,N,Y,Y),
ERET-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_PCR,REN_N,WEN_N,I_X ,SYNC_N,Y,N,Y,N),
FENCE-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_Y,M_FENCE, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_D,N,N,N,N),
FENCE_I-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_I,N,N,N,N),
CFLUSH-> List(Y, N,BR_N, REN_Y,REN_N,A2_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,Y,Y),
MFPCR-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PCR,REN_Y,WEN_N,I_X ,SYNC_N,N,N,Y,N),
MTPCR-> List(Y, N,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_Y,I_X ,SYNC_N,N,N,Y,Y),
RDTIME-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
RDCYCLE-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
RDINSTRET-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_IRT,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
initial vu integration
2012-02-09 06:43:45 +01:00
// Instructions that have not yet been implemented
// Faking these for now so akaros will boot
hook up the vector command queue
2012-02-09 10:28:16 +01:00
//MFFSR-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
//MTFSR-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FLW-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FLD-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FSW-> List(Y, N,BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FSD-> List(Y, N,BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
// Vector Stuff
VVCFGIVL-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_VEC,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y),
VSETVL-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_VEC,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y),
VF-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VMVV-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VMSV-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VFMVV-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
FENCE_L_V-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
FENCE_G_V-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
FENCE_L_CV->List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
FENCE_G_CV->List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VLD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VLW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VLWU-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VLH-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VLHU-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VLB-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VLBU-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VSD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VSW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VSH-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VSB-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VFLD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VFLW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VFSD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VFSW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VLSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VLSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VLSTWU-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VLSTH-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VLSTHU-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VLSTB-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VLSTBU-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VSSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VSSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VSSTH-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VSSTB-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VFLSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VFLSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VFSSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N),
VFSSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N)
initial vu integration
2012-02-09 06:43:45 +01:00
))
hook up the vector command queue
2012-02-09 10:28:16 +01:00
val id_int_val :: id_vec_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: cs0 = cs
initial vu integration
2012-02-09 06:43:45 +01:00
val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_div_fn :: id_wen :: id_sel_wa :: id_sel_wb :: cs1 = cs0
val id_ren_pcr :: id_wen_pcr :: id_irq :: id_sync :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = cs1
val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst, resetVal = Bool(false));
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
add fp loads/stores
2012-02-08 08:54:25 +01:00
val id_raddr3 = io.dpath.inst(16,12);
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
val id_raddr2 = io.dpath.inst(21,17);
val id_raddr1 = io.dpath.inst(26,22);
fix WAW hazard handling
2012-01-02 09:25:11 +01:00
val id_waddr = Mux(id_sel_wa === WA_RA, RA, io.dpath.inst(31,27));
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
Don't replay from EX stage. EX replays are now handled from MEM. We may move them to WB.
2011-12-10 04:42:58 +01:00
val id_console_out_val = id_wen_pcr.toBool && (id_raddr2 === PCR_CONSOLE);
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
Support cache->cpu nacks one cycle after request
2011-12-10 09:42:09 +01:00
val wb_reg_div_mul_val = Reg(resetVal = Bool(false))
add fp loads/stores
2012-02-08 08:54:25 +01:00
val wb_reg_dcache_miss = Reg(io.dmem.resp_miss, resetVal = Bool(false));
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 12:38:59 +01:00
val id_reg_btb_hit = Reg(resetVal = Bool(false));
val id_reg_xcpt_itlb = Reg(resetVal = Bool(false));
val id_reg_xcpt_ma_inst = Reg(resetVal = Bool(false));
use replay to handle I$ misses this eliminates a long path in the fetch stage
2012-01-12 04:20:20 +01:00
val id_reg_icmiss = Reg(resetVal = Bool(false));
move replays to writeback stage
2012-01-18 06:12:31 +01:00
val id_reg_replay = Reg(resetVal = Bool(false));
clean up bypassing/hazard checking a bit
2012-02-07 02:26:45 +01:00
val id_load_use = Wire(){Bool()};
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
val ex_reg_br_type = Reg(){UFix(width = 4)};
val ex_reg_btb_hit = Reg(){Bool()};
fix mul/div deadlock bug If independent multiplies or independent divides were issued back-to-back, the second wouldn't execute, causing the register to be busy forever.
2012-01-31 06:14:28 +01:00
val ex_reg_div_val = Reg(){Bool()};
val ex_reg_mul_val = Reg(){Bool()};
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
val ex_reg_mem_val = Reg(){Bool()};
val ex_reg_mem_cmd = Reg(){UFix(width = 4)};
val ex_reg_mem_type = Reg(){UFix(width = 3)};
add fp loads/stores
2012-02-08 08:54:25 +01:00
val ex_reg_wen = Reg(resetVal = Bool(false));
val ex_reg_fp_wen = Reg(resetVal = Bool(false));
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
val ex_reg_eret = Reg(resetVal = Bool(false));
don't flush pipeline after MFPCR
2012-01-25 03:40:08 +01:00
val ex_reg_replay_next = Reg(resetVal = Bool(false));
added ei and di instructions
2011-11-14 22:48:49 +01:00
val ex_reg_inst_di = Reg(resetVal = Bool(false));
val ex_reg_inst_ei = Reg(resetVal = Bool(false));
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
2011-11-14 13:13:13 +01:00
val ex_reg_flush_inst = Reg(resetVal = Bool(false));
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 12:38:59 +01:00
val ex_reg_xcpt_ma_inst = Reg(resetVal = Bool(false));
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
val ex_reg_xcpt_itlb = Reg(resetVal = Bool(false));
val ex_reg_xcpt_illegal = Reg(resetVal = Bool(false));
val ex_reg_xcpt_privileged = Reg(resetVal = Bool(false));
val ex_reg_xcpt_syscall = Reg(resetVal = Bool(false));
add fp loads/stores
2012-02-08 08:54:25 +01:00
val ex_reg_fp_val = Reg(resetVal = Bool(false));
hook up the vector command queue
2012-02-09 10:28:16 +01:00
val ex_reg_vec_val = Reg(resetVal = Bool(false));
move replays to writeback stage
2012-01-18 06:12:31 +01:00
val ex_reg_replay = Reg(resetVal = Bool(false));
add external memory request interface for vec unit
2012-02-09 07:30:45 +01:00
val ex_reg_load_use = Reg(resetVal = Bool(false));
val ex_reg_ext_mem_val = Reg(resetVal = Bool(false))
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 12:38:59 +01:00
add fp loads/stores
2012-02-08 08:54:25 +01:00
val mem_reg_wen = Reg(resetVal = Bool(false));
val mem_reg_fp_wen = Reg(resetVal = Bool(false));
added ei and di instructions
2011-11-14 22:48:49 +01:00
val mem_reg_inst_di = Reg(resetVal = Bool(false));
val mem_reg_inst_ei = Reg(resetVal = Bool(false));
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
2011-11-14 13:13:13 +01:00
val mem_reg_flush_inst = Reg(resetVal = Bool(false));
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 12:38:59 +01:00
val mem_reg_xcpt_ma_inst = Reg(resetVal = Bool(false));
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
val mem_reg_xcpt_itlb = Reg(resetVal = Bool(false));
val mem_reg_xcpt_illegal = Reg(resetVal = Bool(false));
val mem_reg_xcpt_privileged = Reg(resetVal = Bool(false));
more cache fixes, more test harness debug output
2011-11-14 08:32:18 +01:00
val mem_reg_xcpt_fpu = Reg(resetVal = Bool(false));
hook up the vector command queue
2012-02-09 10:28:16 +01:00
val mem_reg_xcpt_vec = Reg(resetVal = Bool(false));
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
val mem_reg_xcpt_syscall = Reg(resetVal = Bool(false));
Don't replay from EX stage. EX replays are now handled from MEM. We may move them to WB.
2011-12-10 04:42:58 +01:00
val mem_reg_replay = Reg(resetVal = Bool(false));
minor control logic cleanup
2012-01-12 23:19:18 +01:00
val mem_reg_kill = Reg(resetVal = Bool(false));
add external memory request interface for vec unit
2012-02-09 07:30:45 +01:00
val mem_reg_ext_mem_val = Reg(resetVal = Bool(false))
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
2011-11-14 13:13:13 +01:00
add fp loads/stores
2012-02-08 08:54:25 +01:00
val wb_reg_wen = Reg(resetVal = Bool(false));
val wb_reg_fp_wen = Reg(resetVal = Bool(false));
move PCR writes to WB stage
2012-01-03 00:42:39 +01:00
val wb_reg_inst_di = Reg(resetVal = Bool(false));
val wb_reg_inst_ei = Reg(resetVal = Bool(false));
don't flush I$ unless fence.i commits otherwise, we might not make forward progress.
2012-01-27 05:36:31 +01:00
val wb_reg_flush_inst = Reg(resetVal = Bool(false));
move PCR writes to WB stage
2012-01-03 00:42:39 +01:00
val wb_reg_eret = Reg(resetVal = Bool(false));
val wb_reg_exception = Reg(resetVal = Bool(false));
move replays to writeback stage
2012-01-18 06:12:31 +01:00
val wb_reg_replay = Reg(resetVal = Bool(false));
move PCR writes to WB stage
2012-01-03 00:42:39 +01:00
val wb_reg_cause = Reg(){UFix()};
use replay to handle I$ misses this eliminates a long path in the fetch stage
2012-01-12 04:20:20 +01:00
val take_pc = Wire() { Bool() };
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
when (!io.dpath.stalld) {
when (io.dpath.killf) {
move replays to writeback stage
2012-01-18 06:12:31 +01:00
id_reg_btb_hit <== Bool(false);
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 12:38:59 +01:00
id_reg_xcpt_ma_inst <== Bool(false);
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
id_reg_xcpt_itlb <== Bool(false);
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
otherwise{
move replays to writeback stage
2012-01-18 06:12:31 +01:00
id_reg_btb_hit <== io.dpath.btb_hit;
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 12:38:59 +01:00
id_reg_xcpt_ma_inst <== if_reg_xcpt_ma_inst;
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
id_reg_xcpt_itlb <== io.xcpt_itlb;
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
move replays to writeback stage
2012-01-18 06:12:31 +01:00
id_reg_icmiss <== !io.imem.resp_val;
id_reg_replay <== !take_pc && !io.imem.resp_val;
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
made eret instruction take an illegal inst exception when ET is set
2011-11-14 23:35:10 +01:00
// executing ERET when traps are enabled causes an illegal instruction exception (as per ISA sim)
hook up the vector command queue
2012-02-09 10:28:16 +01:00
val illegal_inst =
!(id_int_val.toBool || fpdec.io.valid || id_vec_val.toBool) ||
(id_eret.toBool && io.dpath.status(SR_ET).toBool);
more cache fixes, more test harness debug output
2011-11-14 08:32:18 +01:00
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
when (reset.toBool || io.dpath.killd) {
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
ex_reg_br_type <== BR_N;
ex_reg_btb_hit <== Bool(false);
fix mul/div deadlock bug If independent multiplies or independent divides were issued back-to-back, the second wouldn't execute, causing the register to be busy forever.
2012-01-31 06:14:28 +01:00
ex_reg_div_val <== Bool(false);
ex_reg_mul_val <== Bool(false);
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
ex_reg_mem_val <== Bool(false);
add fp loads/stores
2012-02-08 08:54:25 +01:00
ex_reg_wen <== Bool(false);
ex_reg_fp_wen <== Bool(false);
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
ex_reg_eret <== Bool(false);
don't flush pipeline after MFPCR
2012-01-25 03:40:08 +01:00
ex_reg_replay_next <== Bool(false);
added ei and di instructions
2011-11-14 22:48:49 +01:00
ex_reg_inst_di <== Bool(false);
ex_reg_inst_ei <== Bool(false);
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
2011-11-14 13:13:13 +01:00
ex_reg_flush_inst <== Bool(false);
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 12:38:59 +01:00
ex_reg_xcpt_ma_inst <== Bool(false);
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
ex_reg_xcpt_itlb <== Bool(false);
ex_reg_xcpt_illegal <== Bool(false);
ex_reg_xcpt_privileged <== Bool(false);
ex_reg_xcpt_syscall <== Bool(false);
add fp loads/stores
2012-02-08 08:54:25 +01:00
ex_reg_fp_val <== Bool(false);
hook up the vector command queue
2012-02-09 10:28:16 +01:00
ex_reg_vec_val <== Bool(false);
move replays to writeback stage
2012-01-18 06:12:31 +01:00
ex_reg_replay <== Bool(false);
clean up bypassing/hazard checking a bit
2012-02-07 02:26:45 +01:00
ex_reg_load_use <== Bool(false);
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
otherwise {
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
ex_reg_br_type <== id_br_type;
ex_reg_btb_hit <== id_reg_btb_hit;
fix mul/div to rd=0
2012-02-09 05:11:57 +01:00
ex_reg_div_val <== id_div_val.toBool && id_waddr != UFix(0);
ex_reg_mul_val <== id_mul_val.toBool && id_waddr != UFix(0);
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
ex_reg_mem_val <== id_mem_val.toBool;
arbitrate for LLFU writebacks in MEM stage
2012-02-08 13:21:05 +01:00
ex_reg_wen <== id_wen.toBool && id_waddr != UFix(0);
add fp loads/stores
2012-02-08 08:54:25 +01:00
ex_reg_fp_wen <== fpdec.io.wen;
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
ex_reg_eret <== id_eret.toBool;
don't flush pipeline after MFPCR
2012-01-25 03:40:08 +01:00
ex_reg_replay_next <== id_replay_next.toBool;
added ei and di instructions
2011-11-14 22:48:49 +01:00
ex_reg_inst_di <== (id_irq === I_DI);
ex_reg_inst_ei <== (id_irq === I_EI);
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
2011-11-14 13:13:13 +01:00
ex_reg_flush_inst <== (id_sync === SYNC_I);
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 12:38:59 +01:00
ex_reg_xcpt_ma_inst <== id_reg_xcpt_ma_inst;
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
ex_reg_xcpt_itlb <== id_reg_xcpt_itlb;
more cache fixes, more test harness debug output
2011-11-14 08:32:18 +01:00
ex_reg_xcpt_illegal <== illegal_inst;
made eret instruction take an illegal inst exception when ET is set
2011-11-14 23:35:10 +01:00
ex_reg_xcpt_privileged <== (id_privileged & ~io.dpath.status(SR_S)).toBool;
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
ex_reg_xcpt_syscall <== id_syscall.toBool;
add fp loads/stores
2012-02-08 08:54:25 +01:00
ex_reg_fp_val <== fpdec.io.valid;
hook up the vector command queue
2012-02-09 10:28:16 +01:00
ex_reg_vec_val <== id_vec_val.toBool
don't flush pipeline after MFPCR
2012-01-25 03:40:08 +01:00
ex_reg_replay <== id_reg_replay || ex_reg_replay_next;
clean up bypassing/hazard checking a bit
2012-02-07 02:26:45 +01:00
ex_reg_load_use <== id_load_use;
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
add external memory request interface for vec unit
2012-02-09 07:30:45 +01:00
ex_reg_ext_mem_val <== io.ext_mem.req_val
ex_reg_mem_cmd <== Mux(io.ext_mem.req_val, io.ext_mem.req_cmd, id_mem_cmd).toUFix
ex_reg_mem_type <== Mux(io.ext_mem.req_val, io.ext_mem.req_type, id_mem_type).toUFix
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
val beq = io.dpath.br_eq;
val bne = ~io.dpath.br_eq;
val blt = io.dpath.br_lt;
val bltu = io.dpath.br_ltu;
val bge = ~io.dpath.br_lt;
val bgeu = ~io.dpath.br_ltu;
val br_taken =
(ex_reg_br_type === BR_EQ) & beq |
(ex_reg_br_type === BR_NE) & bne |
(ex_reg_br_type === BR_LT) & blt |
(ex_reg_br_type === BR_LTU) & bltu |
(ex_reg_br_type === BR_GE) & bge |
validate BTB address and use BTB for J/JAL/JR/JALR even if we weren't using the BTB for JR/JALR, we'd need to flush the BTB on FENCE.I and on context switches, but validating its result suffices instead.
2012-01-02 02:04:14 +01:00
(ex_reg_br_type === BR_GEU) & bgeu |
improve id/ex datapath move operand selection into decode stage; simplify bypassing
2012-02-08 15:47:26 +01:00
(ex_reg_br_type === BR_J) |
(ex_reg_br_type === BR_JR); // treat J/JAL/JALR like a taken branch
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
val mem_reg_div_mul_val = Reg(){Bool()};
fixes to exception and dcache miss/blocked handling
2011-11-02 21:32:32 +01:00
val mem_reg_eret = Reg(){Bool()};
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
val mem_reg_mem_val = Reg(){Bool()};
val mem_reg_mem_cmd = Reg(){UFix(width = 4)};
val mem_reg_mem_type = Reg(){UFix(width = 3)};
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
when (reset.toBool || io.dpath.killx) {
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
mem_reg_div_mul_val <== Bool(false);
add fp loads/stores
2012-02-08 08:54:25 +01:00
mem_reg_wen <== Bool(false);
mem_reg_fp_wen <== Bool(false);
fixes to exception and dcache miss/blocked handling
2011-11-02 21:32:32 +01:00
mem_reg_eret <== Bool(false);
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
mem_reg_mem_val <== Bool(false);
added ei and di instructions
2011-11-14 22:48:49 +01:00
mem_reg_inst_di <== Bool(false);
mem_reg_inst_ei <== Bool(false);
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
2011-11-14 13:13:13 +01:00
mem_reg_flush_inst <== Bool(false);
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 12:38:59 +01:00
mem_reg_xcpt_ma_inst <== Bool(false);
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
mem_reg_xcpt_itlb <== Bool(false);
mem_reg_xcpt_illegal <== Bool(false);
mem_reg_xcpt_privileged <== Bool(false);
more cache fixes, more test harness debug output
2011-11-14 08:32:18 +01:00
mem_reg_xcpt_fpu <== Bool(false);
hook up the vector command queue
2012-02-09 10:28:16 +01:00
mem_reg_xcpt_vec <== Bool(false);
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
mem_reg_xcpt_syscall <== Bool(false);
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
}
otherwise {
fix mul/div deadlock bug If independent multiplies or independent divides were issued back-to-back, the second wouldn't execute, causing the register to be busy forever.
2012-01-31 06:14:28 +01:00
mem_reg_div_mul_val <== ex_reg_div_val || ex_reg_mul_val;
add fp loads/stores
2012-02-08 08:54:25 +01:00
mem_reg_wen <== ex_reg_wen;
mem_reg_fp_wen <== ex_reg_fp_wen;
fixes to exception and dcache miss/blocked handling
2011-11-02 21:32:32 +01:00
mem_reg_eret <== ex_reg_eret;
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
mem_reg_mem_val <== ex_reg_mem_val;
added ei and di instructions
2011-11-14 22:48:49 +01:00
mem_reg_inst_di <== ex_reg_inst_di;
mem_reg_inst_ei <== ex_reg_inst_ei;
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
2011-11-14 13:13:13 +01:00
mem_reg_flush_inst <== ex_reg_flush_inst;
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 12:38:59 +01:00
mem_reg_xcpt_ma_inst <== ex_reg_xcpt_ma_inst;
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
mem_reg_xcpt_itlb <== ex_reg_xcpt_itlb;
fixed typo that broke illegal instruction exception
2011-11-13 10:17:33 +01:00
mem_reg_xcpt_illegal <== ex_reg_xcpt_illegal;
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
mem_reg_xcpt_privileged <== ex_reg_xcpt_privileged;
add fp loads/stores
2012-02-08 08:54:25 +01:00
mem_reg_xcpt_fpu <== ex_reg_fp_val && !io.dpath.status(SR_EF).toBool;
hook up the vector command queue
2012-02-09 10:28:16 +01:00
mem_reg_xcpt_vec <== ex_reg_vec_val && !io.dpath.status(SR_EV).toBool;
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
mem_reg_xcpt_syscall <== ex_reg_xcpt_syscall;
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
}
add external memory request interface for vec unit
2012-02-09 07:30:45 +01:00
mem_reg_ext_mem_val <== ex_reg_ext_mem_val;
slight control logic cleanup
2012-01-12 01:56:40 +01:00
mem_reg_mem_cmd <== ex_reg_mem_cmd;
mem_reg_mem_type <== ex_reg_mem_type;
move PCR writes to WB stage
2012-01-03 00:42:39 +01:00
when (io.dpath.killm) {
add fp loads/stores
2012-02-08 08:54:25 +01:00
wb_reg_wen <== Bool(false);
wb_reg_fp_wen <== Bool(false);
move PCR writes to WB stage
2012-01-03 00:42:39 +01:00
wb_reg_eret <== Bool(false);
wb_reg_inst_di <== Bool(false);
wb_reg_inst_ei <== Bool(false);
don't flush I$ unless fence.i commits otherwise, we might not make forward progress.
2012-01-27 05:36:31 +01:00
wb_reg_flush_inst <== Bool(false);
move replays to writeback stage
2012-01-18 06:12:31 +01:00
wb_reg_div_mul_val <== Bool(false);
move PCR writes to WB stage
2012-01-03 00:42:39 +01:00
}
otherwise {
add fp loads/stores
2012-02-08 08:54:25 +01:00
wb_reg_wen <== mem_reg_wen;
wb_reg_fp_wen <== mem_reg_fp_wen;
move PCR writes to WB stage
2012-01-03 00:42:39 +01:00
wb_reg_eret <== mem_reg_eret;
wb_reg_inst_di <== mem_reg_inst_di;
wb_reg_inst_ei <== mem_reg_inst_ei;
don't flush I$ unless fence.i commits otherwise, we might not make forward progress.
2012-01-27 05:36:31 +01:00
wb_reg_flush_inst <== mem_reg_flush_inst;
move replays to writeback stage
2012-01-18 06:12:31 +01:00
wb_reg_div_mul_val <== mem_reg_div_mul_val;
move PCR writes to WB stage
2012-01-03 00:42:39 +01:00
}
fixes for div/mul hazard checking + cleanup
2011-11-02 07:14:34 +01:00
add fp loads/stores
2012-02-08 08:54:25 +01:00
val sboard = new rocketCtrlSboard();
sboard.io.raddra := id_raddr2.toUFix;
sboard.io.raddrb := id_raddr1.toUFix;
sboard.io.raddrc := id_waddr.toUFix;
// scoreboard set (for D$ misses, div, mul)
sboard.io.set := wb_reg_div_mul_val || wb_reg_dcache_miss && wb_reg_wen;
sboard.io.seta := io.dpath.wb_waddr;
sboard.io.clr := io.dpath.sboard_clr;
sboard.io.clra := io.dpath.sboard_clra;
val id_stall_raddr2 = id_renx2.toBool && sboard.io.stalla;
val id_stall_raddr1 = id_renx1.toBool && sboard.io.stallb;
val id_stall_waddr = id_wen.toBool && sboard.io.stallc;
var id_stall_fpu = Bool(false)
if (HAVE_FPU) {
val fp_sboard = new rocketCtrlSboard();
fp_sboard.io.raddra := id_raddr1.toUFix;
fp_sboard.io.raddrb := id_raddr2.toUFix;
fp_sboard.io.raddrc := id_raddr3.toUFix;
fp_sboard.io.raddrd := id_waddr.toUFix;
fp_sboard.io.set := wb_reg_dcache_miss && wb_reg_fp_wen;
fp_sboard.io.seta := io.dpath.wb_waddr;
fp_sboard.io.clr := io.dpath.fp_sboard_clr;
fp_sboard.io.clra := io.dpath.fp_sboard_clra;
id_stall_fpu = fpdec.io.ren1 && fp_sboard.io.stalla ||
fpdec.io.ren2 && fp_sboard.io.stallb ||
fpdec.io.ren3 && fp_sboard.io.stallc ||
fpdec.io.wen && fp_sboard.io.stalld
}
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
// exception handling
added timer interrupt support
2011-11-13 09:27:57 +01:00
// FIXME: verify PC in MEM stage points to valid, restartable instruction
added IPIs and timer interrupts
2011-11-14 12:24:02 +01:00
val p_irq_timer = (io.dpath.status(15).toBool && io.dpath.irq_timer);
val p_irq_ipi = (io.dpath.status(13).toBool && io.dpath.irq_ipi);
val interrupt =
io.dpath.status(SR_ET).toBool && io.dpath.mem_valid &&
((io.dpath.status(15).toBool && io.dpath.irq_timer) ||
(io.dpath.status(13).toBool && io.dpath.irq_ipi));
val interrupt_cause =
Mux(p_irq_ipi, UFix(21,5),
Mux(p_irq_timer, UFix(23,5),
UFix(0,5)));
hellacache now works
2011-12-17 12:26:11 +01:00
minor control logic cleanup
2012-01-12 23:19:18 +01:00
val mem_xcpt_ma_ld = io.xcpt_ma_ld && !mem_reg_kill
val mem_xcpt_ma_st = io.xcpt_ma_st && !mem_reg_kill
val mem_xcpt_dtlb_ld = io.xcpt_dtlb_ld && !mem_reg_kill
val mem_xcpt_dtlb_st = io.xcpt_dtlb_st && !mem_reg_kill
added timer interrupt support
2011-11-13 09:27:57 +01:00
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
val mem_exception =
added timer interrupt support
2011-11-13 09:27:57 +01:00
interrupt ||
hellacache now works
2011-12-17 12:26:11 +01:00
mem_xcpt_ma_ld ||
mem_xcpt_ma_st ||
slight control logic cleanup
2012-01-12 01:56:40 +01:00
mem_xcpt_dtlb_ld ||
mem_xcpt_dtlb_st ||
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
mem_reg_xcpt_illegal ||
mem_reg_xcpt_privileged ||
mem_reg_xcpt_fpu ||
hook up the vector command queue
2012-02-09 10:28:16 +01:00
mem_reg_xcpt_vec ||
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
mem_reg_xcpt_syscall ||
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 12:38:59 +01:00
mem_reg_xcpt_itlb ||
mem_reg_xcpt_ma_inst;
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
val mem_cause =
added timer interrupt support
2011-11-13 09:27:57 +01:00
Mux(interrupt, interrupt_cause, // asynchronous interrupt
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 09:50:09 +01:00
Mux(mem_reg_xcpt_itlb, UFix(1,5), // instruction access fault
Mux(mem_reg_xcpt_illegal, UFix(2,5), // illegal instruction
Mux(mem_reg_xcpt_privileged, UFix(3,5), // privileged instruction
Mux(mem_reg_xcpt_fpu, UFix(4,5), // FPU disabled
Mux(mem_reg_xcpt_syscall, UFix(6,5), // system call
// breakpoint
slight control logic cleanup
2012-01-12 01:56:40 +01:00
Mux(mem_xcpt_ma_ld, UFix(8,5), // misaligned load
Mux(mem_xcpt_ma_st, UFix(9,5), // misaligned store
Mux(mem_xcpt_dtlb_ld, UFix(10,5), // load fault
Mux(mem_xcpt_dtlb_st, UFix(11,5), // store fault
hook up the vector command queue
2012-02-09 10:28:16 +01:00
Mux(mem_reg_xcpt_vec, UFix(12,5), // vector disabled
UFix(0,5)))))))))))); // instruction address misaligned
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 12:38:59 +01:00
Don't replay from EX stage. EX replays are now handled from MEM. We may move them to WB.
2011-12-10 04:42:58 +01:00
// control transfer from ex/mem
validate BTB address and use BTB for J/JAL/JR/JALR even if we weren't using the BTB for JR/JALR, we'd need to flush the BTB on FENCE.I and on context switches, but validating its result suffices instead.
2012-01-02 02:04:14 +01:00
val ex_btb_match = ex_reg_btb_hit && io.dpath.btb_match
improve id/ex datapath move operand selection into decode stage; simplify bypassing
2012-02-08 15:47:26 +01:00
val take_pc_ex = !ex_btb_match && br_taken || ex_reg_btb_hit && !br_taken
move replays to writeback stage
2012-01-18 06:12:31 +01:00
val take_pc_wb = wb_reg_replay || wb_reg_exception || wb_reg_eret;
add external memory request interface for vec unit
2012-02-09 07:30:45 +01:00
take_pc := take_pc_ex || take_pc_wb;
move replays to writeback stage
2012-01-18 06:12:31 +01:00
arbitrate for LLFU writebacks in MEM stage
2012-02-08 13:21:05 +01:00
// replay mem stage PC on a DTLB miss or a long-latency writeback
val mem_ll_wb = io.dpath.mem_wb || io.dpath.mul_result_val || io.dpath.div_result_val
add external memory request interface for vec unit
2012-02-09 07:30:45 +01:00
val dmem_kill_mem = io.dpath.mem_valid && (io.dtlb_miss || io.dmem.resp_nack)
val replay_mem = dmem_kill_mem || mem_reg_wen && mem_ll_wb || mem_reg_replay
val kill_mem = dmem_kill_mem || mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill
val kill_dcache = io.dtlb_miss || mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill
access faults now write badvaddr PCR register with faulting address
2011-11-10 11:46:09 +01:00
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
2011-11-14 13:13:13 +01:00
// replay execute stage PC when the D$ is blocked, when the D$ misses,
// for privileged instructions, and for fence.i instructions
add fp loads/stores
2012-02-08 08:54:25 +01:00
val replay_ex = wb_reg_dcache_miss && ex_reg_load_use || mem_reg_flush_inst ||
fix mul/div deadlock bug If independent multiplies or independent divides were issued back-to-back, the second wouldn't execute, causing the register to be busy forever.
2012-01-31 06:14:28 +01:00
ex_reg_replay || ex_reg_mem_val && !(io.dmem.req_rdy && io.dtlb_rdy) ||
ex_reg_div_val && !io.dpath.div_rdy ||
ex_reg_mul_val && !io.dpath.mul_rdy
fix i$ miss pathology and badvaddr bug
2012-01-18 08:47:35 +01:00
val kill_ex = take_pc_wb || replay_ex
move replays to writeback stage
2012-01-18 06:12:31 +01:00
fix i$ miss pathology and badvaddr bug
2012-01-18 08:47:35 +01:00
mem_reg_replay <== replay_ex && !take_pc_wb;
move replays to writeback stage
2012-01-18 06:12:31 +01:00
mem_reg_kill <== kill_ex;
Don't replay from EX stage. EX replays are now handled from MEM. We may move them to WB.
2011-12-10 04:42:58 +01:00
move replays to writeback stage
2012-01-18 06:12:31 +01:00
wb_reg_replay <== replay_mem && !take_pc_wb;
wb_reg_exception <== mem_exception && !take_pc_wb;
wb_reg_cause <== mem_cause;
fixes to exception and dcache miss/blocked handling
2011-11-02 21:32:32 +01:00
fix when badvaddr is set
2012-01-31 02:15:42 +01:00
val wb_badvaddr_wen = wb_reg_exception && ((wb_reg_cause === UFix(10)) || (wb_reg_cause === UFix(11)))
// write cause to PCR on an exception
io.dpath.exception := wb_reg_exception;
io.dpath.cause := wb_reg_cause;
io.dpath.badvaddr_wen := wb_badvaddr_wen;
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
io.dpath.sel_pc :=
move replays to writeback stage
2012-01-18 06:12:31 +01:00
Mux(wb_reg_exception, PC_EVEC, // exception
Mux(wb_reg_replay, PC_WB, // replay
Mux(wb_reg_eret, PC_PCR, // eret instruction
improve id/ex datapath move operand selection into decode stage; simplify bypassing
2012-02-08 15:47:26 +01:00
Mux(ex_reg_btb_hit && !br_taken, PC_EX4, // mispredicted not taken branch
validate BTB address and use BTB for J/JAL/JR/JALR even if we weren't using the BTB for JR/JALR, we'd need to flush the BTB on FENCE.I and on context switches, but validating its result suffices instead.
2012-01-02 02:04:14 +01:00
Mux(!ex_btb_match && br_taken, PC_BR, // mispredicted taken branch
Mux(io.dpath.btb_hit, PC_BTB, // predicted PC from BTB
improve id/ex datapath move operand selection into decode stage; simplify bypassing
2012-02-08 15:47:26 +01:00
PC_4)))))); // PC+4
validate BTB address and use BTB for J/JAL/JR/JALR even if we weren't using the BTB for JR/JALR, we'd need to flush the BTB on FENCE.I and on context switches, but validating its result suffices instead.
2012-01-02 02:04:14 +01:00
improve id/ex datapath move operand selection into decode stage; simplify bypassing
2012-02-08 15:47:26 +01:00
io.dpath.wen_btb := !ex_btb_match && br_taken;
io.dpath.clr_btb := ex_reg_btb_hit && !br_taken || id_reg_icmiss;
fix i$ miss pathology and badvaddr bug
2012-01-18 08:47:35 +01:00
fix I$ miss replay bug
2012-01-22 05:42:13 +01:00
io.imem.req_val := take_pc_wb || !mem_reg_replay && !ex_reg_replay && (take_pc_ex || !id_reg_replay)
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
fix WAW hazard handling
2012-01-02 09:25:11 +01:00
// stall for RAW/WAW hazards on loads, AMOs, and mul/div in execute stage.
add fp loads/stores
2012-02-08 08:54:25 +01:00
val data_hazard_ex = ex_reg_wen &&
(id_renx1.toBool && id_raddr1 === io.dpath.ex_waddr ||
id_renx2.toBool && id_raddr2 === io.dpath.ex_waddr ||
id_wen.toBool && id_waddr === io.dpath.ex_waddr)
val fp_data_hazard_ex = ex_reg_fp_wen &&
(fpdec.io.ren1 && id_raddr1 === io.dpath.ex_waddr ||
fpdec.io.ren2 && id_raddr2 === io.dpath.ex_waddr ||
fpdec.io.ren3 && id_raddr3 === io.dpath.ex_waddr ||
fpdec.io.wen && id_waddr === io.dpath.ex_waddr)
val id_ex_hazard = data_hazard_ex && (ex_reg_mem_val || ex_reg_div_val || ex_reg_mul_val) ||
fp_data_hazard_ex && ex_reg_mem_val
dcache loads working - 1/2 cycle load/use delay depending on load type
2011-11-02 05:25:52 +01:00
fix WAW hazard handling
2012-01-02 09:25:11 +01:00
// stall for RAW/WAW hazards on LB/LH and mul/div in memory stage.
add fp loads/stores
2012-02-08 08:54:25 +01:00
val mem_mem_cmd_bh =
(mem_reg_mem_type === MT_B) || (mem_reg_mem_type === MT_BU) ||
(mem_reg_mem_type === MT_H) || (mem_reg_mem_type === MT_HU)
val data_hazard_mem = mem_reg_wen &&
(id_renx1.toBool && id_raddr1 === io.dpath.mem_waddr ||
id_renx2.toBool && id_raddr2 === io.dpath.mem_waddr ||
id_wen.toBool && id_waddr === io.dpath.mem_waddr)
val fp_data_hazard_mem = mem_reg_fp_wen &&
(fpdec.io.ren1 && id_raddr1 === io.dpath.mem_waddr ||
fpdec.io.ren2 && id_raddr2 === io.dpath.mem_waddr ||
fpdec.io.ren3 && id_raddr3 === io.dpath.mem_waddr ||
fpdec.io.wen && id_waddr === io.dpath.mem_waddr)
fix mul/wb hazard checks I erroneously assumed that those instructions set id_wen.
2012-02-08 10:56:11 +01:00
val id_mem_hazard = data_hazard_mem && (mem_reg_mem_val && mem_mem_cmd_bh || mem_reg_div_mul_val)
add fp loads/stores
2012-02-08 08:54:25 +01:00
id_load_use := mem_reg_mem_val && (data_hazard_mem || fp_data_hazard_mem)
fix WAW hazard handling
2012-01-02 09:25:11 +01:00
// stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback.
add fp loads/stores
2012-02-08 08:54:25 +01:00
val data_hazard_wb = wb_reg_wen &&
(id_renx1.toBool && id_raddr1 === io.dpath.wb_waddr ||
id_renx2.toBool && id_raddr2 === io.dpath.wb_waddr ||
id_wen.toBool && id_waddr === io.dpath.wb_waddr)
val fp_data_hazard_wb = wb_reg_fp_wen &&
(fpdec.io.ren1 && id_raddr1 === io.dpath.wb_waddr ||
fpdec.io.ren2 && id_raddr2 === io.dpath.wb_waddr ||
fpdec.io.ren3 && id_raddr3 === io.dpath.wb_waddr ||
fpdec.io.wen && id_waddr === io.dpath.wb_waddr)
val id_wb_hazard = data_hazard_wb && (wb_reg_dcache_miss || wb_reg_div_mul_val) ||
fp_data_hazard_wb && wb_reg_dcache_miss
fix WAW hazard handling
2012-01-02 09:25:11 +01:00
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
val ctrl_stalld =
Don't replay from EX stage. EX replays are now handled from MEM. We may move them to WB.
2011-12-10 04:42:58 +01:00
!take_pc &&
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
(
clean up bypassing/hazard checking a bit
2012-02-07 02:26:45 +01:00
id_ex_hazard || id_mem_hazard || id_wb_hazard ||
add fp loads/stores
2012-02-08 08:54:25 +01:00
id_stall_raddr1 || id_stall_raddr2 || id_stall_waddr ||
add external memory request interface for vec unit
2012-02-09 07:30:45 +01:00
id_stall_fpu || io.ext_mem.req_val ||
Don't replay from EX stage. EX replays are now handled from MEM. We may move them to WB.
2011-12-10 04:42:58 +01:00
id_mem_val.toBool && !(io.dmem.req_rdy && io.dtlb_rdy) ||
hellacache now works
2011-12-17 12:26:11 +01:00
((id_sync === SYNC_D) || (id_sync === SYNC_I)) && !io.dmem.req_rdy ||
arbitrate for LLFU writebacks in MEM stage
2012-02-08 13:21:05 +01:00
id_console_out_val && !io.console.rdy
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
);
fix fpga build
2012-01-14 05:04:11 +01:00
val ctrl_stallf = ctrl_stalld;
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
Don't replay from EX stage. EX replays are now handled from MEM. We may move them to WB.
2011-12-10 04:42:58 +01:00
val ctrl_killd = take_pc || ctrl_stalld;
val ctrl_killf = take_pc || !io.imem.resp_val;
moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
2011-11-18 08:50:45 +01:00
don't flush I$ unless fence.i commits otherwise, we might not make forward progress.
2012-01-27 05:36:31 +01:00
io.flush_inst := wb_reg_flush_inst;
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
fix fpga build
2012-01-14 05:04:11 +01:00
io.dpath.stallf := ctrl_stallf;
Don't replay from EX stage. EX replays are now handled from MEM. We may move them to WB.
2011-12-10 04:42:58 +01:00
io.dpath.stalld := ctrl_stalld;
io.dpath.killf := ctrl_killf;
io.dpath.killd := ctrl_killd;
io.dpath.killx := kill_ex;
io.dpath.killm := kill_mem;
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
add fp loads/stores
2012-02-08 08:54:25 +01:00
io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen
fix WAW hazard handling
2012-01-02 09:25:11 +01:00
io.dpath.ren2 := id_renx2.toBool;
io.dpath.ren1 := id_renx1.toBool;
add external memory request interface for vec unit
2012-02-09 07:30:45 +01:00
io.dpath.sel_alu2 := Mux(io.ext_mem.req_val, A2_ZERO, id_sel_alu2)
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
io.dpath.fn_dw := id_fn_dw.toBool;
io.dpath.fn_alu := id_fn_alu;
io.dpath.div_fn := id_div_fn;
io.dpath.div_val := id_div_val.toBool;
io.dpath.mul_fn := id_mul_fn;
io.dpath.mul_val := id_mul_val.toBool;
add external memory request interface for vec unit
2012-02-09 07:30:45 +01:00
io.dpath.ex_ext_mem_val := ex_reg_ext_mem_val;
add fp loads/stores
2012-02-08 08:54:25 +01:00
io.dpath.ex_fp_val:= ex_reg_fp_val;
io.dpath.ex_wen := ex_reg_wen;
io.dpath.mem_wen := mem_reg_wen;
io.dpath.wb_wen := wb_reg_wen;
interface cleanup, major pipeline changes
2011-11-02 01:59:27 +01:00
io.dpath.sel_wa := id_sel_wa.toBool;
io.dpath.sel_wb := id_sel_wb;
io.dpath.ren_pcr := id_ren_pcr.toBool;
io.dpath.wen_pcr := id_wen_pcr.toBool;
moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
2011-11-18 08:50:45 +01:00
io.dpath.id_eret := id_eret.toBool;
move PCR writes to WB stage
2012-01-03 00:42:39 +01:00
io.dpath.wb_eret := wb_reg_eret;
io.dpath.irq_disable := wb_reg_inst_di;
io.dpath.irq_enable := wb_reg_inst_ei;
Don't replay from EX stage. EX replays are now handled from MEM. We may move them to WB.
2011-12-10 04:42:58 +01:00
slight control logic cleanup
2012-01-12 01:56:40 +01:00
io.dtlb_val := ex_reg_mem_val;
minor control logic cleanup
2012-01-12 23:19:18 +01:00
io.dtlb_kill := mem_reg_kill;
add external memory request interface for vec unit
2012-02-09 07:30:45 +01:00
io.dmem.req_val := ex_reg_mem_val || ex_reg_ext_mem_val;
minor control logic cleanup
2012-01-12 23:19:18 +01:00
io.dmem.req_kill := kill_dcache;
Don't replay from EX stage. EX replays are now handled from MEM. We may move them to WB.
2011-12-10 04:42:58 +01:00
io.dmem.req_cmd := ex_reg_mem_cmd;
io.dmem.req_type := ex_reg_mem_type;
add external memory request interface for vec unit
2012-02-09 07:30:45 +01:00
io.ext_mem.resp_nack:= mem_reg_ext_mem_val && (io.dmem.resp_nack || Reg(!io.dmem.req_rdy))
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-26 08:02:47 +02:00
}
}
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