2014-09-12 19:15:04 +02:00
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// See LICENSE for license details.
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2014-09-02 22:51:57 +02:00
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package rocketchip
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2014-08-23 10:26:03 +02:00
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import Chisel._
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2015-07-30 02:56:19 +02:00
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import junctions._
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2016-08-11 02:20:00 +02:00
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import rocket._
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2016-10-04 00:17:36 +02:00
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import diplomacy._
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2016-06-28 22:16:48 +02:00
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import uncore.agents._
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2016-08-11 02:20:00 +02:00
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import uncore.tilelink._
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2016-06-28 22:16:48 +02:00
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import uncore.devices._
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2016-07-07 01:54:58 +02:00
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import uncore.converters._
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2016-09-28 06:27:07 +02:00
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import util._
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2016-08-11 02:20:00 +02:00
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import coreplex._
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2015-06-26 08:17:35 +02:00
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import scala.math.max
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2016-08-02 04:07:03 +02:00
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import scala.collection.mutable.{LinkedHashSet, ListBuffer}
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2016-08-20 03:26:34 +02:00
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import scala.collection.immutable.HashMap
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2015-07-13 23:54:26 +02:00
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import DefaultTestSuites._
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2016-04-22 04:37:08 +02:00
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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2014-08-23 10:26:03 +02:00
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2016-09-11 08:39:29 +02:00
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class BasePlatformConfig extends Config(
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topDefinitions = {
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(pname,site,here) => {
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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2016-09-28 00:11:31 +02:00
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lazy val edgeDataBits = site(EdgeDataBits)
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lazy val edgeDataBeats = (8 * site(CacheBlockBytes)) / edgeDataBits
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pname match {
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//Memory Parameters
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2016-09-28 00:11:31 +02:00
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case EdgeDataBits => 64
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case EdgeIDBits => 5
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case NastiKey => NastiParameters(
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dataBits = edgeDataBits,
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addrBits = site(PAddrBits),
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idBits = site(EdgeIDBits))
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2016-10-09 21:34:10 +02:00
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case TLEmitMonitors => true
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2016-09-27 21:07:02 +02:00
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case TLKey("EdgetoSlave") =>
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site(TLKey("L1toL2")).copy(dataBeats = edgeDataBeats)
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2016-09-27 20:44:11 +02:00
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case TLKey("MCtoEdge") =>
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site(TLKey("L2toMC")).copy(dataBeats = edgeDataBeats)
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2016-09-27 20:44:11 +02:00
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case TLKey("MMIOtoEdge") =>
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site(TLKey("L2toMMIO")).copy(dataBeats = edgeDataBeats)
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2016-09-11 08:39:29 +02:00
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case BuildCoreplex =>
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(c: CoreplexConfig, p: Parameters) => LazyModule(new DefaultCoreplex(c)(p)).module
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case NExtTopInterrupts => 2
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2016-09-24 00:25:58 +02:00
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case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 4)
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2016-09-11 08:39:29 +02:00
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// Note that PLIC asserts that this is > 0.
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case AsyncDebugBus => false
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case IncludeJtagDTM => false
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case AsyncMMIOChannels => false
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case ExtMMIOPorts => Nil
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case NExtMMIOAXIChannels => 0
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case NExtMMIOAHBChannels => 0
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case NExtMMIOTLChannels => 0
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case AsyncBusChannels => false
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case NExtBusAXIChannels => 0
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case HastiId => "Ext"
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case HastiKey("TL") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(TLKey(site(TLId))).dataBits / site(TLKey(site(TLId))).dataBeats)
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case HastiKey("Ext") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = edgeDataBits)
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case AsyncMemChannels => false
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
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case TMemoryChannels => BusType.AXI
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case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case BuildExampleTop =>
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(p: Parameters) => LazyModule(new ExampleTop(p))
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2016-09-10 00:12:05 +02:00
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case SimMemLatency => 0
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case _ => throw new CDEMatchError
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2016-03-15 02:03:33 +01:00
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}
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2015-09-25 18:41:19 +02:00
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}
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2016-09-11 08:39:29 +02:00
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})
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2015-12-16 19:24:57 +01:00
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2016-08-11 02:20:00 +02:00
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class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig)
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class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
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2015-11-21 08:26:28 +01:00
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class DefaultL2Config extends Config(new WithL2Cache ++ new BaseConfig)
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2016-07-05 02:07:58 +02:00
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class DefaultBufferlessConfig extends Config(
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new WithBufferlessBroadcastHub ++ new BaseConfig)
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2015-10-22 03:23:58 +02:00
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class FPGAConfig extends Config (
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2014-10-06 22:43:40 +02:00
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(pname,site,here) => pname match {
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case NAcquireTransactors => 4
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2016-06-08 01:13:01 +02:00
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case _ => throw new CDEMatchError
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2014-09-24 02:05:14 +02:00
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}
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2014-10-06 22:43:40 +02:00
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)
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2014-09-24 02:05:14 +02:00
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2016-08-11 02:20:00 +02:00
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class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
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class DefaultL2FPGAConfig extends Config(
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new WithL2Capacity(64) ++ new WithL2Cache ++ new DefaultFPGAConfig)
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class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
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class WithNMemoryChannels(n: Int) extends Config(
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(pname,site,here) => pname match {
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case NMemoryChannels => Dump("N_MEM_CHANNELS", n)
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2016-06-08 01:13:01 +02:00
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case _ => throw new CDEMatchError
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2016-05-25 20:08:11 +02:00
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}
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)
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2016-08-18 01:31:34 +02:00
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class WithExtMemSize(n: Long) extends Config(
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(pname,site,here) => pname match {
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case ExtMemSize => Dump("MEM_SIZE", n)
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case _ => throw new CDEMatchError
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}
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)
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2016-06-02 01:18:42 +02:00
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class WithAHB extends Config(
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(pname, site, here) => pname match {
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case TMemoryChannels => BusType.AHB
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case NExtMMIOAHBChannels => 1
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})
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2016-07-01 03:20:43 +02:00
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class WithTL extends Config(
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(pname, site, here) => pname match {
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case TMemoryChannels => BusType.TL
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case NExtMMIOTLChannels => 1
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})
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2016-09-03 00:59:16 +02:00
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class WithScratchpads extends Config(new WithNMemoryChannels(0) ++ new WithDataScratchpad(16384))
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2016-06-23 01:08:27 +02:00
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class DefaultFPGASmallConfig extends Config(new WithSmallCores ++ new DefaultFPGAConfig)
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class DefaultSmallConfig extends Config(new WithSmallCores ++ new BaseConfig)
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class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultConfig)
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2015-08-06 21:51:18 +02:00
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2016-06-14 01:24:01 +02:00
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class DualBankConfig extends Config(
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new WithNBanksPerMemChannel(2) ++ new BaseConfig)
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2015-11-19 02:07:01 +01:00
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class DualBankL2Config extends Config(
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new WithNBanksPerMemChannel(2) ++ new WithL2Cache ++ new BaseConfig)
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2015-11-03 05:10:10 +01:00
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2016-06-14 01:24:01 +02:00
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class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new BaseConfig)
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2015-11-19 02:07:01 +01:00
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class DualChannelL2Config extends Config(
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new WithNMemoryChannels(2) ++ new WithL2Cache ++ new BaseConfig)
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2015-11-19 02:07:01 +01:00
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class DualChannelDualBankConfig extends Config(
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new WithNMemoryChannels(2) ++
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new WithNBanksPerMemChannel(2) ++ new BaseConfig)
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2015-11-19 02:07:01 +01:00
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class DualChannelDualBankL2Config extends Config(
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new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(2) ++
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new WithL2Cache ++ new BaseConfig)
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2015-11-19 02:07:01 +01:00
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2016-05-25 20:08:11 +02:00
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class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
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2015-11-21 08:26:28 +01:00
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2016-09-28 00:11:31 +02:00
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class WithEdgeDataBits(dataBits: Int) extends Config(
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(pname, site, here) => pname match {
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case EdgeDataBits => dataBits
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2016-09-16 04:47:18 +02:00
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case _ => throw new CDEMatchError
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2016-07-01 03:20:43 +02:00
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})
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2016-09-28 00:11:31 +02:00
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class Edge128BitConfig extends Config(
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new WithEdgeDataBits(128) ++ new BaseConfig)
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class Edge32BitConfig extends Config(
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new WithEdgeDataBits(32) ++ new BaseConfig)
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2016-07-01 03:20:43 +02:00
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2015-11-21 08:26:28 +01:00
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class SmallL2Config extends Config(
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new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
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new WithL2Capacity(256) ++ new DefaultL2Config)
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2016-01-07 06:38:35 +01:00
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2016-06-14 01:24:01 +02:00
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class SingleChannelBenchmarkConfig extends Config(new WithL2Capacity(256) ++ new DefaultL2Config)
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class DualChannelBenchmarkConfig extends Config(new WithNMemoryChannels(2) ++ new SingleChannelBenchmarkConfig)
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class QuadChannelBenchmarkConfig extends Config(new WithNMemoryChannels(4) ++ new SingleChannelBenchmarkConfig)
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class OctoChannelBenchmarkConfig extends Config(new WithNMemoryChannels(8) ++ new SingleChannelBenchmarkConfig)
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2016-02-18 00:23:30 +01:00
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2016-06-14 01:24:01 +02:00
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class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseConfig)
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2016-02-26 10:33:25 +01:00
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2016-02-29 23:49:18 +01:00
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class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config)
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2016-03-28 22:22:00 +02:00
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2016-06-21 02:58:26 +02:00
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class DualCoreConfig extends Config(
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new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig)
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2016-07-22 20:36:45 +02:00
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class TinyConfig extends Config(
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new WithScratchpads ++
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new WithSmallCores ++ new WithRV32 ++
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2016-07-22 20:36:45 +02:00
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new WithStatelessBridge ++ new BaseConfig)
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2016-08-04 01:33:30 +02:00
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2016-08-19 18:46:43 +02:00
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class WithAsyncDebug extends Config (
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(pname, site, here) => pname match {
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2016-09-16 04:47:18 +02:00
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case AsyncDebugBus => true
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case _ => throw new CDEMatchError
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2016-08-19 18:46:43 +02:00
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}
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)
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class WithJtagDTM extends Config (
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(pname, site, here) => pname match {
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2016-09-16 04:47:18 +02:00
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case IncludeJtagDTM => true
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case _ => throw new CDEMatchError
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2016-08-19 18:46:43 +02:00
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}
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)
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2016-09-28 00:52:13 +02:00
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class WithNoPeripheryArithAMO extends Config (
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(pname, site, here) => pname match {
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case PeripheryBusKey => PeripheryBusConfig(arithAMO = false, beatBytes = 4)
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}
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)
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class With64BitPeriphery extends Config (
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(pname, site, here) => pname match {
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case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 8)
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}
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)
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2016-10-09 21:34:10 +02:00
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class WithTLMonitors extends Config (
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(pname, site, here) => pname match {
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case TLEmitMonitors => true
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case _ => throw new CDEMatchError
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}
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)
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class WithoutTLMonitors extends Config (
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(pname, site, here) => pname match {
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case TLEmitMonitors => false
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case _ => throw new CDEMatchError
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}
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)
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