Henry Cook
1e69a2dc1c
[tilelink2] allow TL monitors to be globally enabled or disabled ( #392 )
2016-10-09 12:34:10 -07:00
Wesley W. Terpstra
f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
Howard Mao
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
Howard Mao
c45cc76cef
Get rid of remaining MemIO code
...
The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.
2016-09-27 16:28:17 -07:00
Wesley W. Terpstra
3926cb936b
rocketchip: add pbus width and AMO With classes ( #357 )
2016-09-27 15:52:13 -07:00
Howard Mao
71a9c78e4b
add WidthAdapter from AXI slave to Coreplex TL slave
2016-09-27 12:48:01 -07:00
Howard Mao
7d6fb950b6
Give TileLink IDs more sensible names
...
* Outermost -> MCtoEdge
* MMIO_Outermost -> MMIOtoEdge
Then the corresponding parameters objects are
* L1toL2 -> innerParams
* L2toMC -> outerMemParams
* L2toMMIO -> outerMMIOParams
* MCtoEdge -> edgeMemParams
* MMIOtoEdge -> edgeMMIOParams
2016-09-27 12:48:01 -07:00
Howard Mao
8a55521b01
move memory width adapter from coreplex to periphery
2016-09-27 12:48:01 -07:00
Wesley W. Terpstra
d175bb314d
Periphery: make bus width and arithmetic atomics configurable ( #337 )
2016-09-23 15:25:58 -07:00
Yunsup Lee
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
Wesley W. Terpstra
fb24e847fd
rocketchip: globals are for sissies
2016-09-15 21:28:56 -07:00
Jack Koenig
f2fe437fa4
Use CDEMatchError for improved performance ( #304 )
2016-09-15 19:47:18 -07:00
Howard Mao
9d9f90646d
allow configuration of simulation memory latency
2016-09-12 12:33:50 -07:00
Yunsup Lee
bb3f514e8d
now able to add periphery devices through traits
...
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
2016-09-10 23:39:29 -07:00
Yunsup Lee
2c000a99da
compartmentalize Top into periphery traits
2016-09-08 02:08:57 -07:00
Andrew Waterman
70cfd7ce13
Make DefaultRV32Config be RV32IMAFCS, not RV32IMC
...
The latter is more the domain of TinyConfig.
2016-09-07 01:58:25 -07:00
Andrew Waterman
9fea4c83da
Add RV32F support
2016-09-07 00:05:39 -07:00
Yunsup Lee
fb05f5a07f
remove parameter ExtIOAddrMapEntries ( #250 )
...
with the AddrMap ordering constraint relaxed, this parameter is no longer needed.
2016-09-07 00:05:00 -07:00
Yunsup Lee
56d81b0034
fix configstring printout with no memory
2016-09-06 10:40:11 -07:00
Andrew Waterman
63679bb019
Add support for L1 data scratchpads instead of caches
...
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).
They are currently limited to single cores without DRAM. We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
2016-09-02 16:22:07 -07:00
Megan Wachs
af364bc7bc
Rename RTC to RTCTick to clarify that it needs to be a Boolean signal, not a Clock type signal
2016-09-02 15:14:39 -07:00
Megan Wachs
8163a6b597
Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications
2016-09-02 11:11:40 -07:00
SeungRyeol Lee
b1ce3b8c98
Add address map entries for exported mmio port.
2016-08-31 06:58:38 +09:00
Megan Wachs
53ee54dbd1
Incorporate feedback to make the NExtPerhipheryInterrupts come from DeviceBlock itself
2016-08-26 10:40:39 -07:00
Megan Wachs
428eed79a1
Allow some External Interrupts to come from Periphery
2016-08-25 14:16:33 -07:00
Megan Wachs
9974626d6a
Merge remote-tracking branch 'origin/master' into HEAD
...
Conflicts:
src/main/scala/rocketchip/TestHarness.scala
2016-08-23 07:34:01 -07:00
Howard Mao
61aa716f44
fix bus axi connections in periphery
2016-08-22 11:57:15 -07:00
Howard Mao
f9ea14b4c2
extra devices should get elaborated in a single build function
2016-08-22 11:57:15 -07:00
Megan Wachs
dd4a50c452
Add JTAG DTM and test support in simulation
...
Initial cut
checkpoint which compiles and runs but there is some off-by-1 in the protocol
Debugging the clock crossing logic
checkpoint which works
Clean up the AsyncMailbox black box
2016-08-19 16:08:17 -07:00
Howard Mao
f4e0e0966c
move rocketchip package sources into its own subdirectory
2016-08-19 13:45:23 -07:00