2014-09-13 00:31:38 +02:00
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// See LICENSE for license details.
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2014-04-23 01:55:35 +02:00
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package uncore
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import Chisel._
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2014-08-23 10:19:36 +02:00
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case object CacheName extends Field[String]
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2014-08-08 21:21:57 +02:00
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case object NSets extends Field[Int]
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case object NWays extends Field[Int]
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2014-08-12 03:35:49 +02:00
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case object BlockOffBits extends Field[Int]
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2014-08-08 21:21:57 +02:00
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case object RowBits extends Field[Int]
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case object WordBits extends Field[Int]
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case object Replacer extends Field[() => ReplacementPolicy]
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2014-05-07 10:51:46 +02:00
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2014-08-12 03:35:49 +02:00
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abstract trait CacheParameters extends UsesParameters {
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val paddrBits = params(PAddrBits)
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val vaddrBits = params(VAddrBits)
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val pgIdxBits = params(PgIdxBits)
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val nSets = params(NSets)
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val blockOffBits = params(BlockOffBits)
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val idxBits = log2Up(nSets)
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val untagBits = blockOffBits + idxBits
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val tagBits = paddrBits - untagBits
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2014-08-12 23:55:44 +02:00
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val nWays = params(NWays)
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2014-08-12 03:35:49 +02:00
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val wayBits = log2Up(nWays)
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val isDM = nWays == 1
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2014-08-12 23:55:44 +02:00
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val wordBits = params(WordBits)
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val wordBytes = wordBits/8
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val wordOffBits = log2Up(wordBytes)
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val rowBits = params(RowBits)
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2014-08-12 03:35:49 +02:00
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val rowWords = rowBits/wordBits
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2014-08-12 23:55:44 +02:00
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val rowBytes = rowBits/8
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2014-08-12 03:35:49 +02:00
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val rowOffBits = log2Up(rowBytes)
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val refillCycles = params(TLDataBits)/rowBits
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}
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abstract class CacheBundle extends Bundle with CacheParameters
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abstract class CacheModule extends Module with CacheParameters
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2014-04-23 01:55:35 +02:00
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abstract class ReplacementPolicy {
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def way: UInt
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def miss: Unit
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def hit: Unit
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}
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2014-08-08 21:21:57 +02:00
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class RandomReplacement(ways: Int) extends ReplacementPolicy {
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2014-04-23 01:55:35 +02:00
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private val replace = Bool()
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replace := Bool(false)
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val lfsr = LFSR16(replace)
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2014-08-08 21:21:57 +02:00
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def way = if(ways == 1) UInt(0) else lfsr(log2Up(ways)-1,0)
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2014-04-23 01:55:35 +02:00
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def miss = replace := Bool(true)
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def hit = {}
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}
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2014-08-12 03:35:49 +02:00
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abstract class Metadata extends CacheBundle {
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val tag = Bits(width = tagBits)
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2014-05-28 22:35:08 +02:00
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val coh: CoherenceMetadata
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2014-04-23 01:55:35 +02:00
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}
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2014-08-12 03:35:49 +02:00
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class MetaReadReq extends CacheBundle {
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val idx = Bits(width = idxBits)
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2014-04-23 01:55:35 +02:00
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}
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2014-08-08 21:21:57 +02:00
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class MetaWriteReq[T <: Metadata](gen: T) extends MetaReadReq {
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2014-08-12 03:35:49 +02:00
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val way_en = Bits(width = nWays)
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2014-05-01 10:44:59 +02:00
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val data = gen.clone
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2014-08-08 21:21:57 +02:00
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override def clone = new MetaWriteReq(gen).asInstanceOf[this.type]
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2014-04-23 01:55:35 +02:00
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}
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2014-08-12 03:35:49 +02:00
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class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
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2014-05-28 22:35:08 +02:00
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val rstVal = makeRstVal()
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2014-04-23 01:55:35 +02:00
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val io = new Bundle {
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2014-04-24 01:24:20 +02:00
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val read = Decoupled(new MetaReadReq).flip
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2014-05-06 21:59:45 +02:00
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val write = Decoupled(new MetaWriteReq(rstVal.clone)).flip
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2014-08-12 03:35:49 +02:00
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val resp = Vec.fill(nWays){rstVal.clone.asOutput}
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2014-04-23 01:55:35 +02:00
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}
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2014-05-06 21:59:45 +02:00
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val metabits = rstVal.getWidth
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2014-08-12 03:35:49 +02:00
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val rst_cnt = Reg(init=UInt(0, log2Up(nSets+1)))
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val rst = rst_cnt < UInt(nSets)
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2014-05-28 22:35:08 +02:00
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val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
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val wdata = Mux(rst, rstVal, io.write.bits.data).toBits
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val wmask = Mux(rst, SInt(-1), io.write.bits.way_en)
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2014-04-23 01:55:35 +02:00
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when (rst) { rst_cnt := rst_cnt+UInt(1) }
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2014-08-12 03:35:49 +02:00
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val tag_arr = Mem(UInt(width = metabits*nWays), nSets, seqRead = true)
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2014-04-23 01:55:35 +02:00
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when (rst || io.write.valid) {
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2014-08-12 03:35:49 +02:00
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tag_arr.write(waddr, Fill(nWays, wdata), FillInterleaved(metabits, wmask))
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2014-04-23 01:55:35 +02:00
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}
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2014-05-28 22:35:08 +02:00
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val tags = tag_arr(RegEnable(io.read.bits.idx, io.read.valid))
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2014-08-12 03:35:49 +02:00
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for (w <- 0 until nWays) {
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2014-05-28 22:35:08 +02:00
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val m = tags(metabits*(w+1)-1, metabits*w)
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2014-05-06 21:59:45 +02:00
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io.resp(w) := rstVal.clone.fromBits(m)
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2014-04-23 01:55:35 +02:00
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}
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io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
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io.write.ready := !rst
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}
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2014-09-30 23:48:02 +02:00
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abstract trait L2HellaCacheParameters extends CacheParameters
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with CoherenceAgentParameters
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abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters
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abstract class L2HellaCacheModule extends Module with L2HellaCacheParameters
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trait HasL2Id extends Bundle with CoherenceAgentParameters {
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val id = UInt(width = log2Up(nTransactors))
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}
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trait HasL2InternalRequestState extends L2HellaCacheBundle {
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val tag_match = Bool()
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val meta = new L2Metadata
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val way_en = Bits(width = nWays)
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}
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object L2Metadata {
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def apply(tag: Bits, coh: MasterMetadata) = {
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val meta = new L2Metadata
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meta.tag := tag
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meta.coh := coh
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meta
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}
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}
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class L2Metadata extends Metadata with L2HellaCacheParameters {
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2014-10-03 10:06:33 +02:00
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val coh = new MasterMetadata()(co) //co.masterMetadataOnFlush.clone
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2014-09-30 23:48:02 +02:00
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}
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class L2MetaReadReq extends MetaReadReq with HasL2Id {
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val tag = Bits(width = tagBits)
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}
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class L2MetaWriteReq extends MetaWriteReq[L2Metadata](new L2Metadata)
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2014-10-15 20:46:35 +02:00
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with HasL2Id {
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override def clone = new L2MetaWriteReq().asInstanceOf[this.type]
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}
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2014-09-30 23:48:02 +02:00
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class L2MetaResp extends L2HellaCacheBundle
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with HasL2Id
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with HasL2InternalRequestState
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class L2MetadataArray extends L2HellaCacheModule {
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val io = new Bundle {
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val read = Decoupled(new L2MetaReadReq).flip
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val write = Decoupled(new L2MetaWriteReq).flip
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val resp = Valid(new L2MetaResp)
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}
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val meta = Module(new MetadataArray(() => L2Metadata(UInt(0), co.masterMetadataOnFlush)))
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meta.io.read <> io.read
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meta.io.write <> io.write
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val s1_clk_en = Reg(next = io.read.fire())
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val s1_tag = RegEnable(io.read.bits.tag, io.read.valid)
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val s1_id = RegEnable(io.read.bits.id, io.read.valid)
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def wayMap[T <: Data](f: Int => T) = Vec((0 until nWays).map(f))
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val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === s1_tag)
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val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && co.isValid(meta.io.resp(w).coh)).toBits
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val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_clk_en)
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val s2_tag_match = s2_tag_match_way.orR
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val s2_hit_coh = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEnable(meta.io.resp(w).coh, s1_clk_en)))
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//val s2_hit = s2_tag_match && tl.co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === tl.co.newStateOnHit(s2_req.cmd, s2_hit_state)
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val replacer = params(Replacer)()
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val s1_replaced_way_en = UIntToOH(replacer.way)
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val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
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val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) =>
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RegEnable(meta.io.resp(w), s1_clk_en && s1_replaced_way_en(w))).toSeq)
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io.resp.valid := Reg(next = s1_clk_en)
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io.resp.bits.id := RegEnable(s1_id, s1_clk_en)
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io.resp.bits.tag_match := s2_tag_match
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io.resp.bits.meta := Mux(s2_tag_match,
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L2Metadata(s2_repl_meta.tag, s2_hit_coh),
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s2_repl_meta)
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io.resp.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
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}
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class L2DataReadReq extends L2HellaCacheBundle with HasL2Id {
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val way_en = Bits(width = nWays)
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val addr = Bits(width = params(TLAddrBits))
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}
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class L2DataWriteReq extends L2DataReadReq {
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val wmask = Bits(width = params(TLWriteMaskBits))
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val data = Bits(width = params(TLDataBits))
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}
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class L2DataResp extends Bundle with HasL2Id {
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val data = Bits(width = params(TLDataBits))
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}
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class L2DataArray extends L2HellaCacheModule {
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val io = new Bundle {
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val read = Decoupled(new L2DataReadReq).flip
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val write = Decoupled(new L2DataWriteReq).flip
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val resp = Valid(new L2DataResp)
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}
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val waddr = io.write.bits.addr
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val raddr = io.read.bits.addr
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val wmask = FillInterleaved(wordBits, io.write.bits.wmask)
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val resp = (0 until nWays).map { w =>
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val array = Mem(Bits(width=params(RowBits)), nSets*refillCycles, seqRead = true)
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when (io.write.bits.way_en(w) && io.write.valid) {
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array.write(waddr, io.write.bits.data, wmask)
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}
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array(RegEnable(raddr, io.read.bits.way_en(w) && io.read.valid))
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}
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io.resp.valid := ShiftRegister(io.read.valid, 2)
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io.resp.bits.id := ShiftRegister(io.read.bits.id, 2)
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io.resp.bits.data := Mux1H(ShiftRegister(io.read.bits.way_en, 2), resp)
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io.read.ready := Bool(true)
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io.write.ready := Bool(true)
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}
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class L2HellaCache(bankId: Int, innerId: String, outerId: String) extends
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CoherenceAgent(innerId, outerId) with L2HellaCacheParameters {
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require(isPow2(nSets))
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require(isPow2(nWays))
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require(refillCycles == 1)
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val tshrfile = Module(new TSHRFile(bankId, innerId, outerId))
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val meta = Module(new L2MetadataArray)
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val data = Module(new L2DataArray)
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tshrfile.io.inner <> io.inner
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tshrfile.io.meta_read <> meta.io.read
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tshrfile.io.meta_write <> meta.io.write
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tshrfile.io.meta_resp <> meta.io.resp
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tshrfile.io.data_read <> data.io.read
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tshrfile.io.data_write <> data.io.write
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tshrfile.io.data_resp <> data.io.resp
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io.outer <> tshrfile.io.outer
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io.incoherent <> tshrfile.io.incoherent
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}
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class TSHRFile(bankId: Int, innerId: String, outerId: String) extends L2HellaCacheModule {
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val io = new Bundle {
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val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip
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val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
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val incoherent = Vec.fill(nClients){Bool()}.asInput
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val meta_read = Decoupled(new L2MetaReadReq)
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val meta_write = Decoupled(new L2MetaWriteReq)
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val meta_resp = Valid(new L2MetaResp).flip
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val data_read = Decoupled(new L2DataReadReq)
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val data_write = Decoupled(new L2DataWriteReq)
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val data_resp = Valid(new L2DataResp).flip
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}
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// Wiring helper funcs
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def doOutputArbitration[T <: Data](out: DecoupledIO[T], ins: Seq[DecoupledIO[T]]) {
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val arb = Module(new RRArbiter(out.bits.clone, ins.size))
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out <> arb.io.out
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arb.io.in zip ins map { case (a, in) => a <> in }
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}
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def doInputRouting[T <: HasL2Id](in: ValidIO[T], outs: Seq[ValidIO[T]]) {
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outs.map(_.bits := in.bits)
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outs.zipWithIndex.map { case (o, i) => o.valid := UInt(i) === in.bits.id }
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}
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// Create TSHRs for outstanding transactions
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val trackerList = (0 until nReleaseTransactors).map { id =>
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Module(new L2VoluntaryReleaseTracker(id, bankId, innerId, outerId))
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} ++ (nReleaseTransactors until nTransactors).map { id =>
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Module(new L2AcquireTracker(id, bankId, innerId, outerId))
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}
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// Propagate incoherence flags
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trackerList.map(_.io.tile_incoherent := io.incoherent.toBits)
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// Handle acquire transaction initiation
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val acquire = io.inner.acquire
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val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
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val block_acquires = any_acquire_conflict
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val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.inner
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alloc_arb.io.in(i).valid := t.acquire.ready
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t.acquire.bits := acquire.bits
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t.acquire.valid := alloc_arb.io.in(i).ready
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}
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acquire.ready := trackerList.map(_.io.inner.acquire.ready).reduce(_||_) && !block_acquires
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alloc_arb.io.out.ready := acquire.valid && !block_acquires
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// Handle probe requests
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doOutputArbitration(io.inner.probe, trackerList.map(_.io.inner.probe))
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// Handle releases, which might be voluntary and might have data
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val release = io.inner.release
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val voluntary = co.isVoluntary(release.bits.payload)
|
|
|
|
val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_)
|
|
|
|
val block_releases = Bool(false)
|
|
|
|
val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)).lastIndexWhere{b: Bool => b}
|
|
|
|
//val release_idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UInt(0)), release.bits.payload.master_xact_id) // TODO: Add merging logic to allow allocated AcquireTracker to handle conflicts, send all necessary grants, use first sufficient response
|
|
|
|
val release_idx = Mux(voluntary, UInt(0), release.bits.payload.master_xact_id)
|
|
|
|
for( i <- 0 until trackerList.size ) {
|
|
|
|
val t = trackerList(i).io.inner
|
|
|
|
t.release.bits := release.bits
|
|
|
|
t.release.valid := release.valid && (release_idx === UInt(i)) && !block_releases
|
|
|
|
}
|
|
|
|
release.ready := Vec(trackerList.map(_.io.inner.release.ready)).read(release_idx) && !block_releases
|
|
|
|
|
|
|
|
// Reply to initial requestor
|
|
|
|
doOutputArbitration(io.inner.grant, trackerList.map(_.io.inner.grant))
|
|
|
|
|
2014-10-03 10:06:33 +02:00
|
|
|
// Free finished transactions on ack
|
|
|
|
val finish = io.inner.finish
|
|
|
|
val finish_idx = finish.bits.payload.master_xact_id
|
|
|
|
trackerList.zipWithIndex.map { case (t, i) =>
|
|
|
|
t.io.inner.finish.valid := finish.valid && finish_idx === UInt(i)
|
|
|
|
}
|
|
|
|
trackerList.map(_.io.inner.finish.bits := finish.bits)
|
|
|
|
finish.ready := Vec(trackerList.map(_.io.inner.finish.ready)).read(finish_idx)
|
2014-09-30 23:48:02 +02:00
|
|
|
|
|
|
|
// Arbitrate for the outer memory port
|
|
|
|
val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size),
|
|
|
|
{case TLId => outerId})
|
|
|
|
outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.outer }
|
|
|
|
io.outer <> outer_arb.io.out
|
|
|
|
|
|
|
|
// Local memory
|
|
|
|
doOutputArbitration(io.meta_read, trackerList.map(_.io.meta_read))
|
|
|
|
doOutputArbitration(io.meta_write, trackerList.map(_.io.meta_write))
|
|
|
|
doOutputArbitration(io.data_read, trackerList.map(_.io.data_read))
|
|
|
|
doOutputArbitration(io.data_write, trackerList.map(_.io.data_write))
|
|
|
|
doInputRouting(io.meta_resp, trackerList.map(_.io.meta_resp))
|
|
|
|
doInputRouting(io.data_resp, trackerList.map(_.io.data_resp))
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
abstract class L2XactTracker(innerId: String, outerId: String) extends L2HellaCacheModule {
|
|
|
|
val io = new Bundle {
|
|
|
|
val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip
|
|
|
|
val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
|
|
|
|
val tile_incoherent = Bits(INPUT, nClients)
|
|
|
|
val has_acquire_conflict = Bool(OUTPUT)
|
|
|
|
val has_release_conflict = Bool(OUTPUT)
|
|
|
|
val meta_read = Decoupled(new L2MetaReadReq)
|
|
|
|
val meta_write = Decoupled(new L2MetaWriteReq)
|
|
|
|
val meta_resp = Valid(new L2MetaResp).flip
|
|
|
|
val data_read = Decoupled(new L2DataReadReq)
|
|
|
|
val data_write = Decoupled(new L2DataWriteReq)
|
|
|
|
val data_resp = Valid(new L2DataResp).flip
|
|
|
|
}
|
|
|
|
|
|
|
|
val c_acq = io.inner.acquire.bits
|
|
|
|
val c_rel = io.inner.release.bits
|
|
|
|
val c_gnt = io.inner.grant.bits
|
|
|
|
val c_ack = io.inner.finish.bits
|
|
|
|
val m_gnt = io.outer.grant.bits
|
|
|
|
|
2014-10-08 07:33:10 +02:00
|
|
|
def mergeData(acq: Acquire, data: UInt): UInt = {
|
|
|
|
//TODO wite mask
|
|
|
|
Mux(co.messageHasData(acq), acq.data, data)
|
|
|
|
}
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends L2XactTracker(innerId, outerId) {
|
2014-10-15 20:46:35 +02:00
|
|
|
val s_idle :: s_meta_read :: s_meta_resp :: s_meta_write :: s_data_write :: s_grant :: s_busy :: Nil = Enum(UInt(), 7)
|
2014-09-30 23:48:02 +02:00
|
|
|
val state = Reg(init=s_idle)
|
|
|
|
val xact = Reg{ new Release }
|
|
|
|
val xact_internal = Reg{ new L2MetaResp }
|
|
|
|
val init_client_id = Reg(init=UInt(0, width = log2Up(nClients)))
|
|
|
|
|
|
|
|
io.has_acquire_conflict := Bool(false)
|
|
|
|
io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) &&
|
|
|
|
(state != s_idle)
|
|
|
|
|
|
|
|
io.outer.grant.ready := Bool(false)
|
|
|
|
io.outer.acquire.valid := Bool(false)
|
2014-10-03 10:06:33 +02:00
|
|
|
|
2014-09-30 23:48:02 +02:00
|
|
|
io.inner.acquire.ready := Bool(false)
|
|
|
|
io.inner.probe.valid := Bool(false)
|
|
|
|
io.inner.release.ready := Bool(false)
|
|
|
|
io.inner.grant.valid := Bool(false)
|
|
|
|
io.inner.grant.bits.header.src := UInt(bankId)
|
|
|
|
io.inner.grant.bits.header.dst := init_client_id
|
2014-10-03 10:06:33 +02:00
|
|
|
io.inner.grant.bits.payload := Grant(co.getGrantType(xact, xact_internal.meta.coh),
|
2014-09-30 23:48:02 +02:00
|
|
|
xact.client_xact_id,
|
|
|
|
UInt(trackerId))
|
|
|
|
|
|
|
|
io.data_read.valid := Bool(false)
|
|
|
|
io.data_write.valid := Bool(false)
|
|
|
|
io.data_write.bits.id := UInt(trackerId)
|
|
|
|
io.data_write.bits.way_en := xact_internal.way_en
|
|
|
|
io.data_write.bits.addr := xact.addr
|
|
|
|
io.data_write.bits.wmask := SInt(-1)
|
|
|
|
io.data_write.bits.data := xact.data
|
|
|
|
io.meta_read.valid := Bool(false)
|
|
|
|
io.meta_read.bits.id := UInt(trackerId)
|
|
|
|
io.meta_read.bits.idx := xact.addr(untagBits-1,blockOffBits)
|
|
|
|
io.meta_read.bits.tag := xact.addr >> UInt(untagBits)
|
|
|
|
io.meta_write.valid := Bool(false)
|
|
|
|
io.meta_write.bits.id := UInt(trackerId)
|
|
|
|
io.meta_write.bits.idx := xact.addr(untagBits-1,blockOffBits)
|
|
|
|
io.meta_write.bits.way_en := xact_internal.way_en
|
|
|
|
io.meta_write.bits.data := xact_internal.meta
|
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
is(s_idle) {
|
|
|
|
io.inner.release.ready := Bool(true)
|
|
|
|
when( io.inner.release.valid ) {
|
|
|
|
xact := c_rel.payload
|
|
|
|
init_client_id := c_rel.header.src
|
2014-10-03 10:06:33 +02:00
|
|
|
state := s_meta_read
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
2014-10-03 10:06:33 +02:00
|
|
|
}
|
2014-09-30 23:48:02 +02:00
|
|
|
is(s_meta_read) {
|
2014-10-03 10:06:33 +02:00
|
|
|
io.meta_read.valid := Bool(true)
|
|
|
|
when(io.meta_read.ready) { state := s_meta_resp }
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
is(s_meta_resp) {
|
|
|
|
when(io.meta_resp.valid) {
|
2014-10-08 07:33:10 +02:00
|
|
|
xact_internal := co.masterMetadataOnRelease(xact,
|
|
|
|
io.meta_resp.bits.meta.coh,
|
|
|
|
init_client_id)
|
|
|
|
state := Mux(io.meta_resp.bits.tag_match,
|
|
|
|
Mux(co.messageHasData(xact), s_data_write, s_meta_write),
|
|
|
|
s_grant)
|
2014-10-03 10:06:33 +02:00
|
|
|
}
|
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
is(s_data_write) {
|
|
|
|
io.data_write.valid := Bool(true)
|
|
|
|
when(io.data_write.ready) { state := s_meta_write }
|
|
|
|
}
|
2014-10-03 10:06:33 +02:00
|
|
|
is(s_meta_write) {
|
|
|
|
io.meta_write.valid := Bool(true)
|
2014-10-08 07:33:10 +02:00
|
|
|
when(io.meta_write.ready) { state := s_grant }
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
is(s_grant) {
|
2014-09-30 23:48:02 +02:00
|
|
|
io.inner.grant.valid := Bool(true)
|
2014-10-03 10:06:33 +02:00
|
|
|
when(io.inner.grant.ready) {
|
2014-10-08 07:33:10 +02:00
|
|
|
state := Mux(co.requiresAckForGrant(c_gnt.payload.g_type),
|
2014-10-03 10:06:33 +02:00
|
|
|
s_busy, s_idle)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_busy) {
|
|
|
|
when(io.inner.finish.valid) { state := s_idle }
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends L2XactTracker(innerId, outerId) {
|
2014-10-08 07:33:10 +02:00
|
|
|
val s_idle :: s_meta_read :: s_meta_resp :: s_probe :: s_data_read_wb :: s_data_resp_wb :: s_outer_write_wb :: s_outer_read :: s_outer_resp :: s_data_read_hit :: s_data_resp_hit :: s_data_write :: s_outer_write_acq :: s_meta_write :: s_grant :: s_busy :: Nil = Enum(UInt(), 16)
|
2014-09-30 23:48:02 +02:00
|
|
|
val state = Reg(init=s_idle)
|
|
|
|
val xact = Reg{ new Acquire }
|
|
|
|
val xact_internal = Reg{ new L2MetaResp }
|
2014-10-15 20:46:35 +02:00
|
|
|
val test = Reg{UInt()}
|
2014-09-30 23:48:02 +02:00
|
|
|
val init_client_id = Reg(init=UInt(0, width = log2Up(nClients)))
|
|
|
|
//TODO: Will need id reg for merged release xacts
|
|
|
|
|
|
|
|
|
2014-10-08 07:33:10 +02:00
|
|
|
val release_count = Reg(init = UInt(0, width = log2Up(nClients)))
|
2014-10-15 20:46:35 +02:00
|
|
|
val pending_probes = Reg(init = co.dir().flush)
|
|
|
|
val curr_p_id = co.dir().next(pending_probes)
|
2014-10-08 07:33:10 +02:00
|
|
|
|
|
|
|
val is_uncached = co.messageIsUncached(xact)
|
|
|
|
val tag_match = xact_internal.tag_match
|
|
|
|
val needs_writeback = co.needsWriteback(xact_internal.meta.coh)
|
|
|
|
val is_hit = co.isHit(xact, xact_internal.meta.coh)
|
|
|
|
val needs_probes = co.requiresProbes(xact.a_type, xact_internal.meta.coh)
|
2014-10-15 20:46:35 +02:00
|
|
|
val c_rel_had_data = Reg(init = Bool(false))
|
|
|
|
val c_rel_was_voluntary = Reg(init = Bool(false))
|
2014-10-08 07:33:10 +02:00
|
|
|
val wb_buffer = Reg{xact.data.clone}
|
|
|
|
|
|
|
|
io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) &&
|
|
|
|
(state != s_idle) //TODO: Also indexes
|
|
|
|
io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) &&
|
|
|
|
(state != s_idle) //TODO: Also indexes?
|
2014-09-30 23:48:02 +02:00
|
|
|
|
2014-10-08 07:33:10 +02:00
|
|
|
val outer_write_acq = Bundle(Acquire(co.getUncachedWriteAcquireType,
|
|
|
|
xact.addr,
|
|
|
|
UInt(trackerId),
|
|
|
|
xact.data), { case TLId => outerId })
|
|
|
|
val outer_write_wb = Bundle(Acquire(co.getUncachedWriteAcquireType,
|
|
|
|
Cat(xact_internal.meta.tag,
|
|
|
|
xact.addr(untagBits-1,blockOffBits)),
|
|
|
|
UInt(trackerId),
|
|
|
|
wb_buffer), { case TLId => outerId })
|
|
|
|
val outer_read = Bundle(Acquire(co.getUncachedReadAcquireType,
|
|
|
|
xact.addr,
|
|
|
|
UInt(trackerId)), { case TLId => outerId })
|
2014-09-30 23:48:02 +02:00
|
|
|
io.outer.acquire.valid := Bool(false)
|
2014-10-08 07:33:10 +02:00
|
|
|
io.outer.acquire.bits.payload := outer_read //default
|
2014-09-30 23:48:02 +02:00
|
|
|
io.outer.acquire.bits.header.src := UInt(bankId)
|
2014-10-08 07:33:10 +02:00
|
|
|
io.outer.grant.ready := Bool(true) //grant.data -> xact.data
|
|
|
|
|
|
|
|
val inner_probe_cacq = Probe(co.getProbeType(xact, xact_internal.meta.coh),
|
|
|
|
xact.addr,
|
|
|
|
UInt(trackerId))
|
|
|
|
val inner_probe_wb = Probe(co.getProbeTypeOnVoluntaryWriteback,
|
|
|
|
xact.addr,
|
|
|
|
UInt(trackerId))
|
|
|
|
//TODO inner_probe_mprb
|
2014-09-30 23:48:02 +02:00
|
|
|
io.inner.probe.valid := Bool(false)
|
|
|
|
io.inner.probe.bits.header.src := UInt(bankId)
|
|
|
|
io.inner.probe.bits.header.dst := curr_p_id
|
2014-10-08 07:33:10 +02:00
|
|
|
io.inner.probe.bits.payload := Mux(needs_writeback,
|
|
|
|
inner_probe_wb,
|
|
|
|
inner_probe_cacq)
|
2014-09-30 23:48:02 +02:00
|
|
|
|
2014-10-08 07:33:10 +02:00
|
|
|
val grant_type = co.getGrantType(xact, xact_internal.meta.coh)
|
2014-09-30 23:48:02 +02:00
|
|
|
io.inner.grant.valid := Bool(false)
|
|
|
|
io.inner.grant.bits.header.src := UInt(bankId)
|
|
|
|
io.inner.grant.bits.header.dst := init_client_id
|
|
|
|
io.inner.grant.bits.payload := Grant(grant_type,
|
|
|
|
xact.client_xact_id,
|
|
|
|
UInt(trackerId),
|
2014-10-08 07:33:10 +02:00
|
|
|
xact.data)
|
2014-09-30 23:48:02 +02:00
|
|
|
|
|
|
|
io.inner.acquire.ready := Bool(false)
|
|
|
|
io.inner.release.ready := Bool(false)
|
|
|
|
|
|
|
|
io.data_read.valid := Bool(false)
|
|
|
|
io.data_read.bits.id := UInt(trackerId)
|
|
|
|
io.data_read.bits.way_en := xact_internal.way_en
|
|
|
|
io.data_read.bits.addr := xact.addr
|
|
|
|
io.data_write.valid := Bool(false)
|
|
|
|
io.data_write.bits.id := UInt(trackerId)
|
|
|
|
io.data_write.bits.way_en := xact_internal.way_en
|
|
|
|
io.data_write.bits.addr := xact.addr
|
|
|
|
io.data_write.bits.wmask := SInt(-1)
|
|
|
|
io.data_write.bits.data := xact.data
|
|
|
|
io.meta_read.valid := Bool(false)
|
|
|
|
io.meta_read.bits.id := UInt(trackerId)
|
|
|
|
io.meta_read.bits.idx := xact.addr(untagBits-1,blockOffBits)
|
|
|
|
io.meta_read.bits.tag := xact.addr >> UInt(untagBits)
|
|
|
|
io.meta_write.valid := Bool(false)
|
|
|
|
io.meta_write.bits.id := UInt(trackerId)
|
|
|
|
io.meta_write.bits.idx := xact.addr(untagBits-1,blockOffBits)
|
|
|
|
io.meta_write.bits.way_en := xact_internal.way_en
|
2014-10-08 07:33:10 +02:00
|
|
|
io.meta_write.bits.data.tag := xact.addr >> UInt(untagBits)
|
|
|
|
io.meta_write.bits.data.coh := xact_internal.meta.coh
|
2014-09-30 23:48:02 +02:00
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
is(s_idle) {
|
|
|
|
io.inner.acquire.ready := Bool(true)
|
|
|
|
when( io.inner.acquire.valid ) {
|
|
|
|
xact := c_acq.payload
|
|
|
|
init_client_id := c_acq.header.src
|
2014-10-08 07:33:10 +02:00
|
|
|
state := s_meta_read
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_meta_read) {
|
|
|
|
io.meta_read.valid := Bool(true)
|
|
|
|
when(io.meta_read.ready) { state := s_meta_resp }
|
|
|
|
}
|
|
|
|
is(s_meta_resp) {
|
|
|
|
when(io.meta_resp.valid) {
|
|
|
|
val coh = io.meta_resp.bits.meta.coh
|
|
|
|
val _tag_match = io.meta_resp.bits.tag_match
|
|
|
|
val _needs_writeback = co.needsWriteback(coh)
|
|
|
|
val _is_hit = co.isHit(xact, coh)
|
|
|
|
val _needs_probes = co.requiresProbes(xact.a_type, coh)
|
|
|
|
xact_internal := io.meta_resp.bits
|
2014-10-15 20:46:35 +02:00
|
|
|
test := UInt(0)
|
2014-10-08 07:33:10 +02:00
|
|
|
when(!_needs_writeback) {
|
2014-10-15 20:46:35 +02:00
|
|
|
// xact_internal.meta.coh := co.masterMetadataOnFlush
|
|
|
|
test := UInt(12)
|
2014-10-08 07:33:10 +02:00
|
|
|
}
|
|
|
|
when(_needs_probes) {
|
|
|
|
pending_probes := coh.sharers
|
2014-10-15 20:46:35 +02:00
|
|
|
release_count := co.dir().count(coh.sharers)
|
2014-10-08 07:33:10 +02:00
|
|
|
c_rel_had_data := Bool(false)
|
|
|
|
c_rel_was_voluntary := Bool(false)
|
|
|
|
}
|
|
|
|
state := Mux(_tag_match,
|
|
|
|
Mux(_is_hit,
|
|
|
|
Mux(_needs_probes, s_probe, s_data_read_hit),
|
|
|
|
Mux(_needs_probes, s_probe, s_outer_read)),
|
|
|
|
Mux(_needs_writeback,
|
|
|
|
Mux(_needs_probes, s_probe, s_data_read_wb),
|
|
|
|
s_outer_read))
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_probe) {
|
2014-10-08 07:33:10 +02:00
|
|
|
val skip = io.tile_incoherent(curr_p_id) ||
|
|
|
|
((curr_p_id === init_client_id) &&
|
|
|
|
!co.requiresSelfProbe(xact.a_type))
|
2014-10-15 20:46:35 +02:00
|
|
|
io.inner.probe.valid := !(co.dir().none(pending_probes) || skip)
|
2014-10-08 07:33:10 +02:00
|
|
|
when(io.inner.probe.ready || skip) {
|
2014-10-15 20:46:35 +02:00
|
|
|
co.dir().pop(pending_probes, curr_p_id)
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
when(skip) { release_count := release_count - UInt(1) }
|
2014-09-30 23:48:02 +02:00
|
|
|
|
2014-10-08 07:33:10 +02:00
|
|
|
// Handle releases, which may have data being written back
|
|
|
|
io.inner.release.ready := Bool(true)
|
2014-09-30 23:48:02 +02:00
|
|
|
when(io.inner.release.valid) {
|
2014-10-15 20:46:35 +02:00
|
|
|
/*
|
2014-10-08 07:33:10 +02:00
|
|
|
xact_internal.meta.coh := co.masterMetadataOnRelease(
|
|
|
|
c_rel.payload,
|
|
|
|
xact_internal.meta.coh,
|
|
|
|
c_rel.header.src)
|
2014-10-15 20:46:35 +02:00
|
|
|
*/
|
2014-09-30 23:48:02 +02:00
|
|
|
when(co.messageHasData(c_rel.payload)) {
|
2014-10-08 07:33:10 +02:00
|
|
|
c_rel_had_data := Bool(true)
|
|
|
|
when(tag_match) {
|
|
|
|
xact.data := mergeData(xact, io.inner.release.bits.payload.data)
|
|
|
|
} .otherwise {
|
|
|
|
wb_buffer := io.inner.release.bits.payload.data
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
}
|
|
|
|
when(co.isVoluntary(c_rel.payload)) {
|
|
|
|
c_rel_was_voluntary := Bool(true)
|
|
|
|
}
|
|
|
|
when(!co.isVoluntary(c_rel.payload)) {
|
|
|
|
release_count := release_count - Mux(skip, UInt(2), UInt(1))
|
2014-09-30 23:48:02 +02:00
|
|
|
when(release_count === UInt(1)) {
|
2014-10-08 07:33:10 +02:00
|
|
|
state := Mux(tag_match,
|
|
|
|
Mux(is_hit,
|
|
|
|
Mux(c_rel_had_data, s_meta_write, s_data_read_hit),
|
|
|
|
s_outer_read),
|
|
|
|
Mux(c_rel_had_data, s_outer_write_wb, s_data_read_wb))
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
is(s_data_read_wb) {
|
|
|
|
io.data_read.valid := Bool(true)
|
|
|
|
when(io.data_read.ready) {
|
|
|
|
state := s_data_resp_wb
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_data_resp_wb) {
|
|
|
|
when(io.data_resp.valid) {
|
2014-10-15 20:46:35 +02:00
|
|
|
wb_buffer := io.data_resp.bits.data
|
2014-10-08 07:33:10 +02:00
|
|
|
state := s_outer_write_wb
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_outer_write_wb) {
|
|
|
|
io.outer.acquire.valid := Bool(true)
|
|
|
|
io.outer.acquire.bits.payload := outer_write_wb
|
|
|
|
when(io.outer.acquire.ready) {
|
|
|
|
state := s_outer_read
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_outer_read) {
|
2014-09-30 23:48:02 +02:00
|
|
|
io.outer.acquire.valid := Bool(true)
|
|
|
|
io.outer.acquire.bits.payload := outer_read
|
|
|
|
when(io.outer.acquire.ready) {
|
2014-10-08 07:33:10 +02:00
|
|
|
state := s_outer_resp
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
is(s_outer_resp) {
|
|
|
|
io.outer.grant.ready := Bool(true)
|
|
|
|
when(io.outer.grant.valid) {
|
|
|
|
xact.data := mergeData(xact, io.outer.grant.bits.payload.data)
|
|
|
|
//TODO: set pending client state in xact_internal.meta.coh
|
|
|
|
state := Mux(co.messageHasData(io.outer.grant.bits.payload),
|
|
|
|
s_data_write, s_data_read_hit)
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
is(s_data_read_hit) {
|
|
|
|
io.data_read.valid := Bool(true)
|
|
|
|
when(io.data_read.ready) {
|
|
|
|
state := s_data_resp_hit
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
is(s_data_resp_hit) {
|
|
|
|
when(io.data_resp.valid) {
|
|
|
|
xact.data := mergeData(xact, io.data_resp.bits.data)
|
|
|
|
state := s_meta_write
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
}
|
|
|
|
is(s_data_write) {
|
|
|
|
io.data_write.valid := Bool(true)
|
|
|
|
when(io.data_write.ready) {
|
|
|
|
state := s_meta_write
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
is(s_meta_write) {
|
|
|
|
io.meta_write.valid := Bool(true)
|
|
|
|
when(io.meta_write.ready) { state := s_grant }
|
|
|
|
}
|
|
|
|
is(s_grant) {
|
|
|
|
io.inner.grant.valid := Bool(true)
|
|
|
|
when(io.inner.grant.ready) {
|
|
|
|
state := Mux(co.requiresAckForGrant(c_gnt.payload.g_type),
|
|
|
|
s_busy, s_idle)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_busy) {
|
|
|
|
when(io.inner.finish.valid) { state := s_idle }
|
|
|
|
}
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
}
|