Add dip switches and clean up top interface

src/main/scala/ip/xilinx/Xilinx.scala

@@ -94,6 +94,26 @@ object PowerOnResetFPGAOnly {
   }
 }
 
+//-------------------------------------------------------------------------
+// ml507 clocks (DCM_ADV)
+//-------------------------------------------------------------------------
+
+class ml507_sys_clock extends BlackBox {
+  val io = new Bundle {
+    val CLKIN_IN  = Clock(INPUT)
+    val CLKFX_OUT = Clock(OUTPUT)
+    val LOCKED_OUT = Bool(OUTPUT)
+  }
+}
+
+class ml507_dvi_clock extends BlackBox {
+  val io = new Bundle {
+    val CLKIN_IN  = Clock(INPUT)
+    val CLKFX_OUT = Clock(OUTPUT)
+    val LOCKED_OUT = Bool(OUTPUT)
+  }
+}
+
 //-------------------------------------------------------------------------
 // vc707_sys_clock_mmcm
 //-------------------------------------------------------------------------

src/main/scala/shell/xilinx/ML507Shell.scala

@@ -0,0 +1,211 @@
+// See LICENSE for license details.
+package sifive.fpgashells.shell.xilinx.ml507shell
+
+import Chisel._
+import chisel3.core.{Input, Output, attach}
+import chisel3.experimental.{RawModule, Analog, withClockAndReset}
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.util.{SyncResetSynchronizerShiftReg, ElaborationArtefacts, HeterogeneousBag}
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.chiplink._
+import sifive.blocks.devices.terminal._
+
+import sifive.fpgashells.ip.xilinx.{PowerOnResetFPGAOnly, sdio_spi_bridge, ml507_dvi_clock, ml507_sys_clock, vc707reset}
+
+//-------------------------------------------------------------------------
+// ML507Shell
+//-------------------------------------------------------------------------
+
+// TODO: trait HasDDR2 { … }
+
+trait HasDebugJTAG { this: ML507Shell =>
+  // JTAG
+  val jtag_TCK             = IO(Input(Clock()))
+  val jtag_TMS             = IO(Input(Bool()))
+  val jtag_TDI             = IO(Input(Bool()))
+  val jtag_TDO             = IO(Output(Bool()))
+
+  def connectDebugJTAG(dut: HasPeripheryDebugModuleImp, fmcxm105: Boolean = true): SystemJTAGIO = {
+    val djtag     = dut.debug.systemjtag.get
+
+    djtag.jtag.TCK := jtag_TCK
+    djtag.jtag.TMS := jtag_TMS
+    djtag.jtag.TDI := jtag_TDI
+    jtag_TDO       := djtag.jtag.TDO.data
+
+    djtag.mfr_id   := p(JtagDTMKey).idcodeManufId.U(11.W)
+
+    djtag.reset    := PowerOnResetFPGAOnly(dut_clock)
+    dut_ndreset    := dut.debug.ndreset
+    djtag
+  }
+}
+
+
+abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
+
+  //-----------------------------------------------------------------------
+  // Interface
+  //-----------------------------------------------------------------------
+
+  // 100Mhz sysclk
+  val sys_clock            = IO(Input(Clock()))
+
+  // active high async reset
+  val reset                = IO(Input(Bool()))
+
+  // LED
+  val led                  = IO(Output(Vec(8, Bool())))
+
+  // DIP switches
+  val dip                  = IO(Input(Vec(8, Bool())))
+
+  // UART
+  val uart_tx              = IO(Output(Bool()))
+  val uart_rx              = IO(Input(Bool()))
+
+  // SDIO
+  val sdio_clk             = IO(Output(Bool()))
+  val sdio_cmd             = IO(Analog(1.W))
+  val sdio_dat             = IO(Analog(4.W))
+
+  // Feedback
+  val clock_led            = IO(Output(Clock()))
+  val reset_led            = IO(Output(Bool()))
+
+  val dvi                  = IO(new TerminalDVIIO)
+
+  //-----------------------------------------------------------------------
+  // Wire declrations
+  //-----------------------------------------------------------------------
+
+  // async resets
+  val sys_reset       = Wire(Bool())
+  val do_reset        = Wire(Bool())
+  val dut_ndreset     = Wire(Bool())
+
+  val dut_clock       = Wire(Clock())
+  val dut_reset       = Wire(Bool())
+
+  val dvi_clock       = Wire(Clock())
+  val dvi_reset       = Wire(Bool())
+
+  val sd_spi_sck      = Wire(Bool())
+  val sd_spi_cs       = Wire(Bool())
+  val sd_spi_dq_i     = Wire(Vec(4, Bool()))
+  val sd_spi_dq_o     = Wire(Vec(4, Bool()))
+
+  val clk_locked      = Wire(Bool())
+
+
+  //-----------------------------------------------------------------------
+  // System reset
+  //-----------------------------------------------------------------------
+
+  // Allow the debug module to reset everything. Resets the MIG
+  sys_reset := reset | dut_ndreset
+
+  //-----------------------------------------------------------------------
+  // Clock generators
+  //-----------------------------------------------------------------------
+
+  // 80 MHz (processor clock)
+  val ml507_sys_clock = Module(new ml507_sys_clock)
+  ml507_sys_clock.io.CLKIN_IN := sys_clock
+  dut_clock := ml507_sys_clock.io.CLKFX_OUT
+
+  // 48 MHz (DVI pixel clock for SDR 640x480x60)
+  val ml507_dvi_clock = Module(new ml507_dvi_clock)
+  ml507_dvi_clock.io.CLKIN_IN := sys_clock
+  dvi_clock := ml507_dvi_clock.io.CLKFX_OUT
+
+  // Clocks locked?
+  clk_locked := ml507_sys_clock.io.LOCKED_OUT &
+                ml507_dvi_clock.io.LOCKED_OUT
+
+  //-----------------------------------------------------------------------
+  // System reset
+  //-----------------------------------------------------------------------
+
+  do_reset             := !clk_locked || sys_reset
+
+  // synchronize async resets
+  val safe_reset = Module(new vc707reset)
+
+  safe_reset.io.areset := do_reset
+  safe_reset.io.clock1 := dut_clock
+  safe_reset.io.clock2 := dut_clock
+  safe_reset.io.clock3 := dvi_clock
+  dvi_reset            := safe_reset.io.reset3
+  safe_reset.io.clock4 := dut_clock
+  dut_reset            := safe_reset.io.reset4
+
+  // Setup feedback
+  clock_led := dut_clock
+  reset_led := dut_reset
+
+  //-----------------------------------------------------------------------
+  // Terminal
+  //-----------------------------------------------------------------------
+
+  def connectTerminal(dut: HasPeripheryTerminalModuleImp): Unit = {
+    dvi <> dut.dvi
+    dut.terminal.clk := dvi_clock
+    dut.terminal.reset := dvi_reset
+  }
+
+  //-----------------------------------------------------------------------
+  // UART
+  //-----------------------------------------------------------------------
+
+  def connectUART(dut: HasPeripheryUARTModuleImp): Unit = {
+    val uartParams = p(PeripheryUARTKey)
+    if (!uartParams.isEmpty) {
+      // uart connections
+      dut.uart(0).rxd := SyncResetSynchronizerShiftReg(uart_rx, 2, init = Bool(true), name=Some("uart_rxd_sync"))
+      uart_tx         := dut.uart(0).txd
+    }
+  }
+
+  //-----------------------------------------------------------------------
+  // SPI
+  //-----------------------------------------------------------------------
+
+  def connectSPI(dut: HasPeripherySPIModuleImp): Unit = {
+    // SPI
+    sd_spi_sck := dut.spi(0).sck
+    sd_spi_cs  := dut.spi(0).cs(0)
+
+    dut.spi(0).dq.zipWithIndex.foreach {
+      case(pin, idx) =>
+        sd_spi_dq_o(idx) := pin.o
+        pin.i            := sd_spi_dq_i(idx)
+    }
+
+    //-------------------------------------------------------------------
+    // SDIO <> SPI Bridge
+    //-------------------------------------------------------------------
+
+    val ip_sdio_spi = Module(new sdio_spi_bridge())
+
+    ip_sdio_spi.io.clk   := dut_clock
+    ip_sdio_spi.io.reset := dut_reset
+
+    // SDIO
+    attach(sdio_dat, ip_sdio_spi.io.sd_dat)
+    attach(sdio_cmd, ip_sdio_spi.io.sd_cmd)
+    sdio_clk := ip_sdio_spi.io.spi_sck
+
+    // SPI
+    ip_sdio_spi.io.spi_sck  := sd_spi_sck
+    ip_sdio_spi.io.spi_cs   := sd_spi_cs
+    sd_spi_dq_i             := ip_sdio_spi.io.spi_dq_i.toBools
+    ip_sdio_spi.io.spi_dq_o := sd_spi_dq_o.asUInt
+  }
+
+}