Alex Solomatnikov
3781d1fb1a
Bug fixes: passing OC WB test
2017-02-03 16:41:59 -08:00
Wesley W. Terpstra
c010a1557a
sifive-blocks: trust diplomacy to get names right
2017-02-01 13:53:54 -08:00
Alex Solomatnikov
2cc1012fa2
Completed Chisel RTL (not tested yet)
2017-01-31 17:20:53 -08:00
Wesley W. Terpstra
535be3e976
spi: work around ucb-bar/chisel3#472
2017-01-31 14:03:14 -08:00
Wesley W. Terpstra
5b6760394d
xilinx ip: adjust to new diplomacy API
2017-01-30 11:33:30 -08:00
Alex Solomatnikov
9d2a173b15
Initial (compilable) version of I2C (no actual logic yet)
2017-01-24 14:58:01 -08:00
Wesley W. Terpstra
d61d86e084
xilinx pcie: put buffers before the outputs to the controller
2017-01-20 22:38:27 -08:00
Wesley W. Terpstra
c68e44ec55
mig: track change to Blind port API in rocket
2017-01-19 19:53:03 -08:00
Wesley W. Terpstra
45c491cd69
LazyModule: provide Parameters
...
This tracks PR #478 in rocketchip.
2016-12-07 13:21:20 -08:00
Wesley W. Terpstra
1443834186
xilinx pcie: bytes, not bits
...
This bug amazingly compiled correctly and ran correctly!
It was saved by the AXIFragmenter which turned the "narrow burst" into
individual beats that then got converted to 64b in TileLink land via
inspection of the mask bits.
The consequence is that AXI bus mastering proceeded at one word per
DDR round-trip. Now it is one cache line per DDR round-trip. When we
get L2 back in the design, it should really fly!
2016-12-06 16:13:12 -08:00
Wesley W. Terpstra
ca7555bd4d
RegMapFIFO: amoor.w can do thread-safe TX
2016-12-02 17:48:17 -08:00
Richard Xia
b8ecb7853b
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
SiFive
7916ef5249
Initial commit.
2016-11-29 04:08:44 -08:00
