| .. |
|
arbiter.scala
|
Use HeaderlessTileLinkIO
|
2015-04-13 15:58:10 -07:00 |
|
btb.scala
|
Rename some params, use refactored TileLink
|
2015-02-01 20:37:31 -08:00 |
|
consts.scala
|
Renamed PCR to CSR
|
2015-04-11 02:16:44 -07:00 |
|
core.scala
|
Merge branch 'master' of github.com:ucb-bar/rocket into rocc-fpu-port
|
2015-04-06 13:48:44 -07:00 |
|
csr.scala
|
Removed unnecessary signal in CSRIO
|
2015-04-11 02:20:34 -07:00 |
|
ctrl.scala
|
Rename dmem.sret signal to more accurate invalidate_lr
|
2015-04-11 02:26:33 -07:00 |
|
decode.scala
|
fix decodelogic bug for bitwidths >= 64 s/1L/BigInt(1)/
|
2015-03-10 10:28:05 -07:00 |
|
dpath_alu.scala
|
Rename some params, use refactored TileLink
|
2015-02-01 20:37:31 -08:00 |
|
dpath.scala
|
Renamed PCR to CSR
|
2015-04-11 02:16:44 -07:00 |
|
fpu.scala
|
update rocc port to use fdiv/sqrt
|
2015-04-07 15:02:02 -07:00 |
|
icache.scala
|
Merge branch 'retimeable-frontend' into rocc-fpu-port
|
2015-04-22 14:23:52 -07:00 |
|
instructions.scala
|
Merge [shm]call into ecall, [shm]ret into eret
|
2015-03-17 02:24:41 -07:00 |
|
multiplier.scala
|
Rename some params, use refactored TileLink
|
2015-02-01 20:37:31 -08:00 |
|
nbdcache.scala
|
simplify ClientMetadata.makeRelease
|
2015-04-20 10:46:24 -07:00 |
|
package.scala
|
New privileged ISA implementation
|
2015-03-14 02:49:07 -07:00 |
|
ptw.scala
|
Update PTE format to reflect reserved bits
|
2015-04-04 15:19:15 -07:00 |
|
rocc.scala
|
Merge branch 'master' into rocc-fpu-port
|
2015-04-19 15:00:00 -07:00 |
|
tile.scala
|
HeaderlessTileLinkIO -> ClientTileLinkIO
|
2015-04-17 16:56:53 -07:00 |
|
tlb.scala
|
New virtual memory implementation (Sv39)
|
2015-03-27 16:20:59 -07:00 |
|
util.scala
|
moved ecc lib to uncore
|
2015-04-13 15:58:10 -07:00 |
