riscv/rocket-chip
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  • 5fc44bbcda Add externalIn and externalOut property to Nodes that indicates whether the edges are external or not. (#554) Jacob Chang 2017-02-10 10:19:22 -08:00
  • e8c8d2af71 Heterogeneous Tiles (#550) Henry Cook 2017-02-09 13:59:09 -08:00
  • f9acd4988c Merge pull request #551 from edwardcwang/configdoc Henry Cook 2017-02-09 11:56:38 -08:00
  • fc7838ff7b Merge branch 'master' into configdoc Henry Cook 2017-02-09 10:09:30 -08:00
  • fbefbb5549 Merge pull request #552 from ucb-bar/fix-abs-func Henry Cook 2017-02-09 10:09:16 -08:00
  • 25db3d36c4 Update config override documentation Edward Wang 2017-02-08 15:26:01 -08:00
  • 307e0ca9c0 Fix up Absolute value. As of ucb-bar/chisel#491 and 32885ac, abs now returns the same type as its argument. Add a cast to UInt. Jim Lawson 2017-02-08 15:00:43 -08:00
  • 69f4c1a144 AddressDecoder: support AddressSets with infinite bits (#547) Wesley W. Terpstra 2017-02-04 15:59:50 -08:00
  • 71f2445c62 Merge pull request #546 from ucb-bar/dev-zero Wesley W. Terpstra 2017-02-03 19:49:56 -08:00
  • d1744a5667 coreplex: zero memory channels is also allowed Wesley W. Terpstra 2017-02-03 19:00:08 -08:00
  • a3e56cfa5e rocketchip: add Zero device to the memory subsystem Wesley W. Terpstra 2017-02-03 17:18:20 -08:00
  • b240505a15 rocketchip: move memory channel Xbar from coreplex to rocketchip Wesley W. Terpstra 2017-02-03 16:55:44 -08:00
  • fc9ea62d38 HeterogeneousBag: a handy container for differently parameterized bundles Wesley W. Terpstra 2017-02-03 16:21:33 -08:00
  • 7afe383db3 Ecc: detect uncorrectable errors also for SEC Wesley W. Terpstra 2017-02-03 16:21:09 -08:00
  • 7aba066e67 tilelink2: add TLZero; /dev/zero suitable for putting behind locked cache ways Wesley W. Terpstra 2017-02-03 16:20:27 -08:00
  • 93b2fa197e Artefact output (#545) Wesley W. Terpstra 2017-02-02 19:24:55 -08:00
  • 094b3bc2b1 Merge pull request #544 from ucb-bar/jchang Jacob Chang 2017-02-02 14:56:23 -08:00
  • 83a83c778a Added range function in IdRange Jacob Chang 2017-02-02 10:35:35 -08:00
  • 8225676a86 For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN Andrew Waterman 2017-02-01 22:40:55 -08:00
  • 75edf42323 Set xPIE=1 on xRET Andrew Waterman 2017-02-01 22:40:01 -08:00
  • b2ee5e7d38 Merge pull request #540 from ucb-bar/dedup Wesley W. Terpstra 2017-01-31 17:16:43 -08:00
  • 9ca8f514c0 rocket: creating Bundles in an object also break dedup! Wesley W. Terpstra 2017-01-31 14:45:11 -08:00
  • e1577bb06e chisel3: bump chisel3 for work deduplication Wesley W. Terpstra 2017-01-31 13:55:21 -08:00
  • e5af59db68 rocketchip: work-around ucb-bar/chisel3#472 Wesley W. Terpstra 2017-01-31 13:54:02 -08:00
  • 9c0cc6fdf4 Merge pull request #537 from ucb-bar/l2-banks-together Wesley W. Terpstra 2017-01-30 15:39:04 -08:00
  • dc66c8857f diplomacy: be more robust using Java introspection Wesley W. Terpstra 2017-01-30 14:25:12 -08:00
  • 280af9684b BankedL2Config: use the same LazyModule for all L2 banks Wesley W. Terpstra 2017-01-30 14:02:59 -08:00
  • b567a2a356 Merge pull request #536 from ucb-bar/diplomacy-star-nodes Henry Cook 2017-01-30 11:19:33 -08:00
  • f7f52cc722 diplomacy: restore Monitor functionality Wesley W. Terpstra 2017-01-29 17:25:14 -08:00
  • 972953868c uncore: switch to new diplomacy Node API Wesley W. Terpstra 2017-01-29 15:17:52 -08:00
  • 4d646939b0 diplomacy: make flexible-port adapters possible Wesley W. Terpstra 2017-01-29 13:55:53 -08:00
  • 24ee7f45f5 rocketchip: pass variable l1tol2 connections into coreplex Wesley W. Terpstra 2017-01-29 11:16:00 -08:00
  • d5fa159063 diplomacy: add :*= and :=* to support flexible # of edges Wesley W. Terpstra 2017-01-28 21:20:34 -08:00
  • 03f2fe02ac coreplex: support rational crossing to L2 (#534) Wesley W. Terpstra 2017-01-27 17:09:43 -08:00
  • 61fbe62112 Ignore the built firrtl.jar. (#532) Richard Xia 2017-01-27 13:04:15 -08:00
  • 19c58630d2 Merge pull request #533 from ucb-bar/rational-crossing Wesley W. Terpstra 2017-01-26 22:30:04 -08:00
  • 830d01329d RationalCrossing: add some documentation Wesley W. Terpstra 2017-01-26 21:27:34 -08:00
  • fc3b72084f tilelink2: add a rational clock crossing adapter Wesley W. Terpstra 2017-01-26 15:15:48 -08:00
  • 4b70386393 AsyncCrossing: disambiguate the file name Wesley W. Terpstra 2017-01-26 14:32:27 -08:00
  • 5cf4b0632d RationalCrossing: clock crossing between related clock domains Wesley W. Terpstra 2017-01-26 14:31:12 -08:00
  • 1285fa909f Bump chisel and firrtl (#531) Jack Koenig 2017-01-26 17:29:26 -08:00
  • 3c1dac8c68 Match chisel3 userootunmanageddir - use RootProject/lib as unmanagedBase. (#526) Jim Lawson 2017-01-26 11:11:14 -08:00
  • 0fe2899c74 [tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit (#528) Henry Cook 2017-01-25 12:10:49 -08:00
  • d1dedd25e7 Merge pull request #529 from ucb-bar/physical-optimization Wesley W. Terpstra 2017-01-24 18:59:07 -08:00
  • 6ff35a387a tilelink2: disable A=>D bypass in ToAXI4 whenever possible Wesley W. Terpstra 2017-01-23 18:03:29 -08:00
  • 64e1de751d axi4: add a minLatency parameter Wesley W. Terpstra 2017-01-23 17:54:27 -08:00
  • 46cdfc2b45 diplomacy: find names of LazyModules also in Seq() member values (#527) Wesley W. Terpstra 2017-01-24 18:10:37 -08:00
  • 3fc55298ef coreplex: provide coherence managers with geometry information Wesley W. Terpstra 2017-01-22 11:06:20 -08:00
  • d4b3a0f0be diplomacy: support given bits in AddressDecoder Wesley W. Terpstra 2017-01-22 00:58:55 -08:00
  • c0b6d31377 tilelink2: Delayer adapter useful for unit tests Wesley W. Terpstra 2017-01-21 16:52:40 -08:00
  • b3ef146805 Merge pull request #523 from ucb-bar/buffer-move Wesley W. Terpstra 2017-01-21 14:53:51 -08:00
  • 38c9ddffcc BankedL2: move TLFilter BEFORE coherence manager Wesley W. Terpstra 2017-01-21 13:23:07 -08:00
  • dcadd5a006 coreplex: move TLBuffers for L2 and socBus Wesley W. Terpstra 2017-01-20 22:23:36 -08:00
  • e8ce32a156 Merge pull request #515 from ucb-bar/cache-cork Wesley W. Terpstra 2017-01-19 20:00:51 -08:00
  • 9dc7f180b6 diplomacy: support zero-port Nodes Wesley W. Terpstra 2017-01-19 18:36:39 -08:00
  • c0496fab29 regression: disable build that times out on Travis Wesley W. Terpstra 2017-01-19 18:34:31 -08:00
  • 5d70265e86 rocket: L1 only needs cache-line transfer sizes Wesley W. Terpstra 2017-01-19 17:35:17 -08:00
  • 3a5e5a65f8 coreplex: support multiple memory channels via diplomatic trickery Wesley W. Terpstra 2017-01-19 14:42:02 -08:00
  • e7b35b4bb6 diplomacy: support multiple ports behind a BlindNode Wesley W. Terpstra 2017-01-19 14:25:34 -08:00
  • 258abc5629 coreplex: re-enable stateless L2 config Wesley W. Terpstra 2017-01-19 13:51:50 -08:00
  • 4bdb2e5d68 tilelink2 Monitor: ReleaseAck source does not count Wesley W. Terpstra 2017-01-17 20:39:24 -08:00
  • fbf1073586 tilelink2: CacheCork - terminate caching Wesley W. Terpstra 2017-01-17 18:52:47 -08:00
  • bf7823f1c8 tilelink2: split suportsAcquire into T and B variants Wesley W. Terpstra 2017-01-17 18:52:16 -08:00
  • e03ba637f4 [regression] remove FancyMemTest (timing out) Henry Cook 2017-01-19 12:49:58 -08:00
  • c1b7c84f09 [rocket] bugfix: RoccExampleConfig looks up PAddrBits too early Henry Cook 2017-01-18 18:15:24 -08:00
  • e0411c6cde [coreplex] bugfix: re-enable multicore configs via WithNCores Henry Cook 2017-01-18 17:50:14 -08:00
  • 307f938b88 [rocket] bugfix: fixes #517 Henry Cook 2017-01-18 12:48:58 -08:00
  • 4fe75965a0 Merge pull request #518 from ucb-bar/dtm_regression Megan Wachs 2017-01-18 14:39:53 -08:00
  • e22b01a6fa jtag_dtm: Update regression to run and pass. Megan Wachs 2017-01-18 12:08:13 -08:00
  • 1b31dfa700 Update sbt to 13.12 (#514) Henry Cook 2017-01-17 16:26:22 -08:00
  • 9a6634cd40 Add TLBuffers on the L1 backends and blind exit points (#513) Henry Cook 2017-01-17 11:57:23 -08:00
  • 74b6a8d02b Refactor Tile to use cake pattern (#502) Henry Cook 2017-01-16 18:24:08 -08:00
  • 622e311962 Fix emulator argument processing for unknown DTM arguments (#498) Minux Ma 2017-01-16 16:42:45 -05:00
  • 8157cf1ede Perform integer division when parsing rocketchip.DefaultConfig.conf (#493) GuzTech 2017-01-14 01:40:02 +01:00
  • 52bb6cd9d9 Configs: use a uniform syntax without Match exceptions (#507) Wesley W. Terpstra 2017-01-13 14:41:19 -08:00
  • b448387899 Merge pull request #508 from ucb-bar/jchang Jacob Chang 2017-01-13 10:09:50 -08:00
  • 59eb7c24ee Add iterator function to LazyModule to iterate over all nodes Jacob Chang 2017-01-12 15:20:32 -08:00
  • f1cb06142e bump tools Andrew Waterman 2017-01-05 18:09:57 -08:00
  • 71c4b000b3 Don't special-case power-of-2 replacement policy for BTB Andrew Waterman 2017-01-05 18:08:12 -08:00
  • c531093898 Fix bug introduced with Fuzzer when nOperations is power of 2 (#492) Jacob Chang 2016-12-15 19:10:53 -08:00
  • 4471e0de27 Merge pull request #494 from ucb-bar/diplomatic-apb Wesley W. Terpstra 2016-12-15 17:45:20 -08:00
  • a9b264e582 ahb: lower hsel when idle to save power Wesley W. Terpstra 2016-12-15 14:24:39 -08:00
  • 16febe7e94 apb: add a TileLink to APB bridge and unittest it Wesley W. Terpstra 2016-12-15 14:16:01 -08:00
  • ed091f55e6 apb: diplomatic APB framework Wesley W. Terpstra 2016-12-15 12:10:04 -08:00
  • 4d87d07343 Merge pull request #491 from ucb-bar/ahb-hready-high Wesley W. Terpstra 2016-12-15 02:50:15 +00:00
  • a5b8fc2317 RegisterRouterTest: start up with 0 in registers to make VIP testing easier Wesley W. Terpstra 2016-12-14 15:38:08 -08:00
  • 9d50704b64 ahb: don't violate spec with SRAM fuzzing Wesley W. Terpstra 2016-12-14 14:53:54 -08:00
  • 1a0021b818 Merge pull request #489 from ucb-bar/jchang_test Jacob Chang 2016-12-13 18:46:58 -08:00
  • ebd075d279 Merge branch 'master' into jchang_test Jacob Chang 2016-12-13 15:30:49 -08:00
  • 7e794212d9 Cleanup emulator.cc, use getopt, add help text (#487) Schuyler Eldridge 2016-12-13 17:29:57 -05:00
  • 2dd9e522a0 Merge branch 'master' into jchang_test Jacob Chang 2016-12-12 20:02:53 -08:00
  • 540502f96d Convert frontend and icache to diplomacy/tl2 (#486) Henry Cook 2016-12-12 17:38:55 -08:00
  • 531f3684ed Removing module list for merging. (will need to create iterator in future) Jacob Chang 2016-12-12 16:25:31 -08:00
  • ec425a1d14 Merge with Head Jacob Chang 2016-12-12 16:18:37 -08:00
  • b28c0936a0 Merge remote-tracking branch 'origin/master' into jchang_test Jacob Chang 2016-12-12 16:18:14 -08:00
  • aae9b23036 Update with paratermized LazyModule Jacob Chang 2016-12-12 16:16:56 -08:00
  • 5244fc8433 Bump torture to get updated submodule URL. (#488) Richard Xia 2016-12-12 13:47:33 -08:00
  • c981f8b4f3 More travis job re-balancing (#481) Henry Cook 2016-12-11 22:02:46 -08:00
  • 762afcd54a Merge remote-tracking branch 'origin/master' into jchang_test Jacob Chang 2016-12-09 16:56:49 -08:00
  • 4c3083c181 Remove unnecessary val Jacob Chang 2016-12-09 16:44:30 -08:00