Merge pull request #489 from ucb-bar/jchang_test
Changes made to diplomacy for feature support + bug fix in Fragmenter and fuzzer + support infinite traffic in fuzzer
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1a0021b818
@ -95,6 +95,24 @@ class TLEdge(
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staticHasData(x).map(Bool(_)).getOrElse(opdata)
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}
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def opcode(x: TLDataChannel): UInt = {
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x match {
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case a: TLBundleA => a.opcode
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case b: TLBundleB => b.opcode
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case c: TLBundleC => c.opcode
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case d: TLBundleD => d.opcode
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}
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}
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def param(x: TLDataChannel): UInt = {
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x match {
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case a: TLBundleA => a.param
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case b: TLBundleB => b.param
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case c: TLBundleC => c.param
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case d: TLBundleD => d.param
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}
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}
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def size(x: TLDataChannel): UInt = {
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x match {
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case a: TLBundleA => a.size
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@ -14,7 +14,7 @@ import scala.math.{min,max}
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// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
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// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
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// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
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class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(implicit p: Parameters) extends LazyModule
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class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false)(implicit p: Parameters) extends LazyModule
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{
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require (isPow2 (maxSize))
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require (isPow2 (minSize))
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@ -32,7 +32,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(impli
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TransferSizes.none
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def mapManager(m: TLManagerParameters) = m.copy(
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supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
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supportsLogical = expandTransfer(m.supportsLogical),
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supportsLogical = shrinkTransfer(m.supportsLogical),
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supportsGet = expandTransfer(m.supportsGet),
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supportsPutFull = expandTransfer(m.supportsPutFull),
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supportsPutPartial = expandTransfer(m.supportsPutPartial),
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@ -109,9 +109,13 @@ class TLFuzzer(
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val dataBits = edge.bundle.dataBits
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// Progress through operations
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val num_reqs = Reg(init = UInt(nOperations-1, log2Up(nOperations)))
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val num_resps = Reg(init = UInt(nOperations-1, log2Up(nOperations)))
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io.finished := num_resps === UInt(0)
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val num_reqs = Reg(init = UInt(nOperations, log2Up(nOperations)))
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val num_resps = Reg(init = UInt(nOperations, log2Up(nOperations)))
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if (nOperations>0) {
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io.finished := num_resps === UInt(0)
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} else {
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io.finished := Bool(false)
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}
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// Progress within each operation
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val a = out.a.bits
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@ -180,7 +184,11 @@ class TLFuzzer(
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UInt("b101") -> hbits))
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// Wire both the used and un-used channel signals
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out.a.valid := legal && alloc.valid && num_reqs =/= UInt(0)
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if (nOperations>0) {
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out.a.valid := legal && alloc.valid && num_reqs =/= UInt(0)
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} else {
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out.a.valid := legal && alloc.valid
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}
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out.a.bits := bits
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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@ -191,12 +199,14 @@ class TLFuzzer(
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inc := !legal || req_done
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inc_beat := !legal || out.a.fire()
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when (out.a.fire() && a_last) {
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num_reqs := num_reqs - UInt(1)
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}
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if (nOperations>0) {
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when (out.a.fire() && a_last) {
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num_reqs := num_reqs - UInt(1)
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}
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when (out.d.fire() && d_last) {
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num_resps := num_resps - UInt(1)
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when (out.d.fire() && d_last) {
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num_resps := num_resps - UInt(1)
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}
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}
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}
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}
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@ -13,14 +13,14 @@ abstract class TLMonitorBase(args: TLMonitorArgs) extends LazyModule()(args.p)
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{
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implicit val sourceInfo = args.sourceInfo
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def legalize(bundle: TLBundleSnoop, edge: TLEdge): Unit
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def legalize(bundle: TLBundleSnoop, edge: TLEdge, reset: Bool): Unit
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = args.gen().asInput
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}
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legalize(io.in, args.edge())
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legalize(io.in, args.edge(), reset)
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}
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}
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@ -427,7 +427,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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inflight := (inflight | a_set) & ~d_clr
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}
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def legalize(bundle: TLBundleSnoop, edge: TLEdge) {
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def legalize(bundle: TLBundleSnoop, edge: TLEdge, reset: Bool) {
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legalizeFormat (bundle, edge)
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legalizeMultibeat (bundle, edge)
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legalizeSourceUnique(bundle, edge)
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2
torture
2
torture
@ -1 +1 @@
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Subproject commit b95d8ea3b2273d2a95e421de0d78ab1b280c96b0
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Subproject commit 77195ab12aefc373ca688e0a9c4d710c13191341
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