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Merge pull request #489 from ucb-bar/jchang_test

Changes made to diplomacy for feature support + bug fix in Fragmenter and fuzzer + support infinite traffic in fuzzer
This commit is contained in:
Jacob Chang 2016-12-13 18:46:58 -08:00 committed by GitHub
commit 1a0021b818
5 changed files with 43 additions and 15 deletions

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@ -95,6 +95,24 @@ class TLEdge(
staticHasData(x).map(Bool(_)).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size

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@ -14,7 +14,7 @@ import scala.math.{min,max}
// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(implicit p: Parameters) extends LazyModule
class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false)(implicit p: Parameters) extends LazyModule
{
require (isPow2 (maxSize))
require (isPow2 (minSize))
@ -32,7 +32,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(impli
TransferSizes.none
def mapManager(m: TLManagerParameters) = m.copy(
supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
supportsLogical = expandTransfer(m.supportsLogical),
supportsLogical = shrinkTransfer(m.supportsLogical),
supportsGet = expandTransfer(m.supportsGet),
supportsPutFull = expandTransfer(m.supportsPutFull),
supportsPutPartial = expandTransfer(m.supportsPutPartial),

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@ -109,9 +109,13 @@ class TLFuzzer(
val dataBits = edge.bundle.dataBits
// Progress through operations
val num_reqs = Reg(init = UInt(nOperations-1, log2Up(nOperations)))
val num_resps = Reg(init = UInt(nOperations-1, log2Up(nOperations)))
io.finished := num_resps === UInt(0)
val num_reqs = Reg(init = UInt(nOperations, log2Up(nOperations)))
val num_resps = Reg(init = UInt(nOperations, log2Up(nOperations)))
if (nOperations>0) {
io.finished := num_resps === UInt(0)
} else {
io.finished := Bool(false)
}
// Progress within each operation
val a = out.a.bits
@ -180,7 +184,11 @@ class TLFuzzer(
UInt("b101") -> hbits))
// Wire both the used and un-used channel signals
out.a.valid := legal && alloc.valid && num_reqs =/= UInt(0)
if (nOperations>0) {
out.a.valid := legal && alloc.valid && num_reqs =/= UInt(0)
} else {
out.a.valid := legal && alloc.valid
}
out.a.bits := bits
out.b.ready := Bool(true)
out.c.valid := Bool(false)
@ -191,12 +199,14 @@ class TLFuzzer(
inc := !legal || req_done
inc_beat := !legal || out.a.fire()
when (out.a.fire() && a_last) {
num_reqs := num_reqs - UInt(1)
}
if (nOperations>0) {
when (out.a.fire() && a_last) {
num_reqs := num_reqs - UInt(1)
}
when (out.d.fire() && d_last) {
num_resps := num_resps - UInt(1)
when (out.d.fire() && d_last) {
num_resps := num_resps - UInt(1)
}
}
}
}

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@ -13,14 +13,14 @@ abstract class TLMonitorBase(args: TLMonitorArgs) extends LazyModule()(args.p)
{
implicit val sourceInfo = args.sourceInfo
def legalize(bundle: TLBundleSnoop, edge: TLEdge): Unit
def legalize(bundle: TLBundleSnoop, edge: TLEdge, reset: Bool): Unit
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = args.gen().asInput
}
legalize(io.in, args.edge())
legalize(io.in, args.edge(), reset)
}
}
@ -427,7 +427,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
inflight := (inflight | a_set) & ~d_clr
}
def legalize(bundle: TLBundleSnoop, edge: TLEdge) {
def legalize(bundle: TLBundleSnoop, edge: TLEdge, reset: Bool) {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeSourceUnique(bundle, edge)

@ -1 +1 @@
Subproject commit b95d8ea3b2273d2a95e421de0d78ab1b280c96b0
Subproject commit 77195ab12aefc373ca688e0a9c4d710c13191341