riscv/rocket-chip
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  • 4c595d175c Refactor package hierarchy and remove legacy bus protocol implementations (#845) Henry Cook 2017-07-07 10:48:16 -07:00
  • c28c23150d Merge pull request #850 from freechipsproject/plic_undefZero Megan Wachs 2017-07-06 18:39:10 -07:00
  • 76a1ae667f PLIC: (undefZero=true) Don't allow addresses to alias Megan Wachs 2017-07-06 17:57:08 -07:00
  • a0cbc376b4 Merge pull request #849 from freechipsproject/l2-tlb Andrew Waterman 2017-07-06 13:03:06 -07:00
  • e1cc0a0a0e Mask debug interrupts similarly to other interrupts (#847) Andrew Waterman 2017-07-06 12:03:24 -07:00
  • b2351c5fbf Use consistent casing Andrew Waterman 2017-07-06 11:16:56 -07:00
  • be4eceec0d Fix stupid D$ probe bug Andrew Waterman 2017-07-06 00:26:32 -07:00
  • 90a7d6a343 Add L2 TLB option Andrew Waterman 2017-07-05 23:53:52 -07:00
  • 438abc76d2 Handle TL errors in L1 I$ Andrew Waterman 2017-07-05 23:40:52 -07:00
  • 988caf5e34 Merge pull request #848 from freechipsproject/revert-839-bump-firrtl Megan Wachs 2017-07-05 22:32:45 -07:00
  • 029886d0d5 Revert "Bump firrtl" Megan Wachs 2017-07-05 21:13:47 -07:00
  • f6880555df Merge pull request #839 from freechipsproject/bump-firrtl Jack Koenig 2017-07-05 14:59:58 -07:00
  • 734a178e4e Merge pull request #846 from freechipsproject/travis-delete-caches Megan Wachs 2017-07-05 13:52:26 -07:00
  • 94262ea950 Update README_TRAVIS.md Megan Wachs 2017-07-05 11:45:04 -07:00
  • 84c2bf5504 Update README_TRAVIS.md Megan Wachs 2017-07-05 11:40:36 -07:00
  • bb4452435f Bump Firrtl to get const prop registers and name improvements Jack Koenig 2017-07-05 10:44:18 -07:00
  • ec9fbe26d8 Merge pull request #843 from freechipsproject/tag-ecc Andrew Waterman 2017-07-04 16:20:11 -07:00
  • 0ef45fac9b Add tag ECC to D$ Andrew Waterman 2017-06-30 00:45:29 -07:00
  • e9752f76ae Improve probe state machine Andrew Waterman 2017-06-28 15:24:58 -07:00
  • 85f37146d5 Merge pull request #842 from freechipsproject/fesvr-multi Megan Wachs 2017-07-03 15:31:41 -07:00
  • ddd2b2236d bump riscv-tools/riscv-fesvr to pick up multicore fixes Megan Wachs 2017-07-03 13:23:27 -07:00
  • 3d28c0182d travis: add a branch whitelist with just 'master'. Megan Wachs 2017-06-28 23:10:00 -07:00
  • ee9789eb68 Merge pull request #840 from freechipsproject/fix-dcache-exception-assignment-order Richard Xia 2017-06-30 18:50:49 -07:00
  • 5b46350bc3 Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment. Richard Xia 2017-06-30 17:44:16 -07:00
  • 69ab3626ca Merge pull request #837 from freechipsproject/plic_recode Megan Wachs 2017-06-30 16:05:32 -07:00
  • 8c92c50d85 plic: make assertion comment right Megan Wachs 2017-06-30 14:25:09 -07:00
  • f31ae008f3 plic: Clean up comments and simplify checking Megan Wachs 2017-06-30 14:15:26 -07:00
  • 76f8de75e3 plic: comment tidying Megan Wachs 2017-06-30 12:51:09 -07:00
  • 3da26b0aa8 plic: Add some assertions to check one-hot assumptions Megan Wachs 2017-06-30 12:32:58 -07:00
  • 85ac8d588c Excise the last instance of run-bmarks-test (#836) Ben Keller 2017-06-30 11:50:40 -07:00
  • 237689b799 Merge pull request #838 from freechipsproject/more_plic Megan Wachs 2017-06-30 11:06:27 -07:00
  • 367d4aebe6 Set complete unconditionally Wesley W. Terpstra 2017-06-30 10:15:53 -07:00
  • 4e9f65b2ef Simplify logic further and bugfix Wesley W. Terpstra 2017-06-30 10:07:39 -07:00
  • e8e709c941 plic: Use same recoding technique on complete as well as claim Megan Wachs 2017-06-30 08:36:00 -07:00
  • 3dca2bc4a3 gah Wesley W. Terpstra 2017-06-30 01:07:29 -07:00
  • e43b7accf9 Fix compile error and eliminate wasteful wires Wesley W. Terpstra 2017-06-30 01:06:02 -07:00
  • 834bcf6b7e PLIC: simplify some scala code Megan Wachs 2017-06-29 19:35:15 -07:00
  • eae4fe1469 plic: Recode to use the knowledge that only one interrupt can be claimed at a time. Megan Wachs 2017-06-29 19:09:57 -07:00
  • e3c7bb3b1f SRAM: MemoryDevices use .reg (not .reg("mem")) (#835) Wesley W. Terpstra 2017-06-29 19:07:12 -07:00
  • ae6971b6db Merge pull request #834 from freechipsproject/resumereq-race Megan Wachs 2017-06-29 13:38:20 -07:00
  • 0668f13d99 debug: Fix race between resumereq and resumeack Megan Wachs 2017-06-29 12:27:23 -07:00
  • 7dae3388e1 Merge pull request #830 from freechipsproject/flip-dts-idtim Wesley W. Terpstra 2017-06-29 00:18:19 -07:00
  • 5edc4546e3 rocket: add dtim and itim refs to cpus Wesley W. Terpstra 2017-06-28 21:40:01 -07:00
  • 7d6f8d48f2 Revert "rocket: link dtim to its cpu" Wesley W. Terpstra 2017-06-28 21:28:16 -07:00
  • fbcd6f0eb2 Revert "rocket: link itim to its cpu" Wesley W. Terpstra 2017-06-28 21:28:08 -07:00
  • 6e5a4c687f diplomacy: a type of connect that always disables monitors (#828) Henry Cook 2017-06-28 21:48:10 -07:00
  • 992b480c74 Merge pull request #825 from freechipsproject/debug_wfi Megan Wachs 2017-06-28 21:28:51 -07:00
  • 5002d2accf Merge pull request #827 from freechipsproject/dts-improvements Wesley W. Terpstra 2017-06-28 17:45:06 -07:00
  • 39b06a917f bump riscv-tools for fesvr-dont-die Megan Wachs 2017-06-28 16:38:02 -07:00
  • 66489ffa13 rom+sram: add a compatible field Wesley W. Terpstra 2017-06-28 15:41:20 -07:00
  • ca3030cba3 dcache: fix a gender inversion bug introduced in #826 Wesley W. Terpstra 2017-06-28 15:38:21 -07:00
  • 02aa80a958 TLZero: include a version number Wesley W. Terpstra 2017-06-28 15:12:46 -07:00
  • 48390ed604 rocket: link itim to its cpu Wesley W. Terpstra 2017-06-28 14:53:09 -07:00
  • e6c2d446cc rocket: link dtim to its cpu Wesley W. Terpstra 2017-06-28 14:45:46 -07:00
  • 3f6d5110cd rocket: dtim is not a dcache Wesley W. Terpstra 2017-06-28 14:15:05 -07:00
  • bca3db0866 diplomacy: add RWXC permissions also to ResourceMappings Wesley W. Terpstra 2017-06-28 14:07:40 -07:00
  • 5436be54ff periphery: use SimpleBus for mmio ports Wesley W. Terpstra 2017-06-28 13:58:06 -07:00
  • 171e1a4c05 diplomacy: add SimpleBus to describe bridges Wesley W. Terpstra 2017-06-28 13:47:03 -07:00
  • 84dc23c215 devices: add reg-names to most devices Wesley W. Terpstra 2017-06-28 13:01:40 -07:00
  • 0bf46edb6c diplomacy: support reg-names in DTS output Wesley W. Terpstra 2017-06-28 12:40:43 -07:00
  • 852f03282f rocket: give itim and dtim a compatible field for drivers to match Wesley W. Terpstra 2017-06-28 12:00:44 -07:00
  • 6c2b770605 plic: do not output #address-cells Wesley W. Terpstra 2017-06-07 13:49:51 -07:00
  • 936096dd42 Merge pull request #826 from freechipsproject/tlb2 Andrew Waterman 2017-06-28 13:51:24 -07:00
  • 35b89d8023 bump riscv-tools for fesvr-don't-die Megan Wachs 2017-06-28 13:36:53 -07:00
  • b9a934ae28 Support eccBytes > 1 Andrew Waterman 2017-06-28 02:06:52 -07:00
  • 8e4be40efc Propagate wb_reg_rs2 for sfence ASID Andrew Waterman 2017-06-27 12:46:49 -07:00
  • 2077e4190b Make log more sensible for long-latency operations Andrew Waterman 2017-06-26 15:31:11 -07:00
  • 6f8fdff762 Basic L1 D$ ECC support Andrew Waterman 2017-06-21 00:44:36 -07:00
  • 6100600179 Minor D$ code cleanup Andrew Waterman 2017-06-21 02:19:13 -07:00
  • 9c78ac4d78 Add grouped method to AugmentedUInt, like Seq.grouped Andrew Waterman 2017-06-21 01:35:41 -07:00
  • 8989f5654c Add swizzle method to Encoding Andrew Waterman 2017-06-21 00:44:13 -07:00
  • 3e04a99f61 Refactor frontend exception passing Andrew Waterman 2017-06-08 17:44:48 -07:00
  • cc2f87c214 Forbid S-mode execution from user memory Andrew Waterman 2017-06-08 17:22:51 -07:00
  • 8aa16a11f3 Reduce D$ access energy when refill width > access width Andrew Waterman 2017-06-08 17:13:01 -07:00
  • 25f585f2a9 Remove unused signal from TLB interface Andrew Waterman 2017-06-08 11:21:44 -07:00
  • d5f80df0ae Allow speculative I$ refill to cacheable regions Andrew Waterman 2017-06-07 18:15:33 -07:00
  • 3fc75c2714 debug: report UNSUPPORTED more consistently. Allow haltreq/resumereq to be R as well as W. Megan Wachs 2017-06-27 17:40:58 -07:00
  • e1fe0f245b debug: Don't reset debugint register, as none of the interrupt registers are. Megan Wachs 2017-06-27 14:10:13 -07:00
  • 136e4b6c27 debug: use consistent coding style (Reg(init ... ) vs RegInit) Megan Wachs 2017-06-27 13:39:44 -07:00
  • 3b9550ede3 debug: correctly declare reg_debugint Megan Wachs 2017-06-27 13:38:02 -07:00
  • 56839b2c62 debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec) Megan Wachs 2017-06-27 13:34:55 -07:00
  • 665c2a349c Correct Debug + WFI Interactions Megan Wachs 2017-06-27 13:31:29 -07:00
  • c9cfe46604 rocket,Rocket: fix type mismatch (#819) Zihao Yu 2017-06-28 02:22:08 +08:00
  • 8d07d0af38 Merge pull request #820 from freechipsproject/bump-firrtl Jack Koenig 2017-06-26 18:47:50 -07:00
  • 66f64a9759 tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters (#822) Wesley W. Terpstra 2017-06-26 17:54:17 -07:00
  • e461e0f796 Bump firrtl to get constant propagation improvements Jack 2017-06-25 23:59:40 -07:00
  • 72c46e6c05 Merge pull request #818 from sashimi-yzh/faster-verilator-compile Andrew Waterman 2017-06-26 11:39:42 -07:00
  • fc85a3ce02 emulator,Makefile-verilator: add --output-split-cfuncs flag Zihao Yu 2017-06-26 14:29:29 +08:00
  • 7a0655ae88 Merge pull request #816 from freechipsproject/reduce-axi-queues Wesley W. Terpstra 2017-06-23 18:31:41 -07:00
  • 8ca6c10994 tilelink2: ToAXI4 can strip off low source ID bits Wesley W. Terpstra 2017-06-23 16:59:55 -07:00
  • feecfb53ed axi4: Deinterleaver need not make a Q for an unused AXI id Wesley W. Terpstra 2017-06-23 16:01:31 -07:00
  • 9bea7c1c58 Merge pull request #815 from freechipsproject/reduce-others Wesley W. Terpstra 2017-06-23 12:13:48 -07:00
  • 2d8b2f4edd ReduceOthers: remove constants from the balanced AND tree Wesley W. Terpstra 2017-06-23 00:28:05 -07:00
  • ad4b454b49 isp: passthru based on edgesOut = edgesIn (#814) Henry Cook 2017-06-22 21:23:49 -07:00
  • 48611266fa diplomacy: use ReduceOthers in the RegMapper Wesley W. Terpstra 2017-06-22 19:43:47 -07:00
  • 11d1cb02eb util ReduceOthers produces nlogn cost ready-valid logic Wesley W. Terpstra 2017-06-22 19:43:20 -07:00
  • 1f18a37f01 Merge pull request #813 from freechipsproject/scottj97-patch-1 Scott Johnson 2017-06-22 13:33:15 -07:00
  • 1f137cb9ff Merge pull request #800 from ss2783/patch-1 Jack Koenig 2017-06-22 12:34:41 -07:00
  • aced18b3bb Move RoCC interface to Diplomacy and TL2 (#807) Colin Schmidt 2017-06-22 12:07:09 -07:00
  • bd803d278a Update Readme: rocket-chip uses Travis, not Jenkins Scott Johnson 2017-06-22 10:16:10 -07:00