Gleb Gagarin
fca2e7f9aa
Bumped riscv-tools/riscv-isa-sim
2017-11-15 19:15:47 -08:00
Wesley W. Terpstra
61ef560c75
tilelink: don't pollute TLParamters with AtomicAutomata's implementation ( #1111 )
2017-11-14 17:49:10 -08:00
Wesley W. Terpstra
8b79f0394e
Merge pull request #1105 from freechipsproject/axi4-xbar
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axi4: add an Xbar
2017-11-14 16:18:23 -08:00
Wesley W. Terpstra
509a48c9c9
TLToAXI4: block TL early source re-use before it goes to AXI4 ( #1110 )
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This is a follow-up to PR #1108 .
Rather than increasing the number of transactions we allow to be inflight,
instead just block TL when early source re-use happens. This is a better
fix since it means we don't pay mostly wasted downstream hardware to handle
an additional transaction inflight that almost never happens.
2017-11-14 16:08:43 -08:00
Wesley W. Terpstra
e370934c50
AXI4Xbar: reduce number of special cases
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
9004ecdf25
unittest: include AXI4Xbar in regression
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
5875017956
axi4: add an Xbar
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
72c89f7e30
axi4: add a Filter suitable for manipulating test visibility
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
bfc0ba679a
axi4: add a Delayer for unit tests
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
1902ba063a
Filter: can claim to be out-of-order when you are not
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
58a93e2100
AXI4SRAM: handy helper object
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
353ddffc11
RAMModel: add a convenience object
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
7cfb69e2d5
Queue: silence some warnings
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
147fad6387
Fix AXI4 FIFO ordering for masters with early source reuse ( #1108 )
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* TLToAXI4: fix WaR for single-source FIFO masters
* TLToAXI4: fix potential counter overflow => WaR hazard
If you have a FIFO master with 2^n-1 sources that performs early
source re-use, the old code could potentially break FIFO order.
2017-11-13 20:32:09 -08:00
Henry Cook
7098ebf439
rocket: fix itim GetPropertyByHartId ( #1109 )
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needs to use RocketTileParams.hartid instead of zipWithIndex
2017-11-13 19:25:20 -08:00
Andrew Waterman
b317735319
Merge pull request #1106 from freechipsproject/bump-tools
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bump tools for .align 2 fix in riscv-tests
2017-11-11 23:36:28 -08:00
Andrew Waterman
f0a0687589
bump tools for .align 2 fix in riscv-tests
2017-11-11 19:13:59 -08:00
Wesley W. Terpstra
0cfa801bfc
coreplex: allow MMIO to be misaligned ( #1103 )
2017-11-10 15:12:28 -08:00
Wesley W. Terpstra
a061b16ee3
coreplex: fix typo ( #1104 )
2017-11-10 15:11:56 -08:00
Andrew Waterman
35d377d122
Merge pull request #1100 from freechipsproject/disable-local-amos
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Provide option to support AMOs only on I/O, not DTIM/D$
2017-11-09 21:20:55 -08:00
Andrew Waterman
4ebca73d59
Provide option to support AMOs only on I/O, not DTIM/D$
2017-11-09 17:45:53 -08:00
Andrew Waterman
efdb418559
Merge pull request #1098 from freechipsproject/frontend
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Frontend improvements
2017-11-09 17:44:38 -08:00
Wesley W. Terpstra
50ce3f5086
Merge pull request #1097 from freechipsproject/itim-error
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More ITIM error-handling improvements
2017-11-09 00:17:48 -08:00
Andrew Waterman
d0c6cbba6b
Improve frontend branch prediction
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- Put correctness responsibility on Frontend, not IBuf, for improved
separation of concerns. Frontend must detect case that the BTB
predicts a taken branch in the middle of an instruction.
- Pass BTB information down pipeline unconditionally, fixing case that
screws up the branch history when the BTB misses and the instruction
is misaligned.
- Remove jumpInFrontend option; it's now unconditional.
- Default to one-bit counters in the BHT. For tiny BHTs like these, it's
more resource efficient to have a larger index space than to have
hysteresis.
2017-11-09 00:00:56 -08:00
Andrew Waterman
bb9d8264e2
"Correct" ITIM uncorrectable errors
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This permits forward progress when a core wants to handle its own
uncorrectable ITIM errors. Previously, another core had to do it.
2017-11-08 22:15:03 -08:00
Andrew Waterman
5c1b34d854
Don't report a TL error if overwriting a whole ITIM word
2017-11-08 22:15:03 -08:00
Andrew Waterman
9b16d25861
Fix reporting of ITIM error addresses on slave-port accesses
2017-11-08 22:15:03 -08:00
Palmer Dabbelt
9441c29d92
Merge pull request #1096 from freechipsproject/tools
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Bump riscv-tools, for a new toolchain release
2017-11-08 17:20:28 -08:00
Wesley W. Terpstra
b59880fe8e
Fragmenter: add an option for earlyAck only on PutFulls ( #1095 )
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Fragmenter: add a third case for earlyAck (PutFulls only)
It seems quite common to have a device that is backed by ECC. When
performing a multibeat PutPartial, these devices can exhibit their
first error on the last beat (if it had an incomplete write mask
for that beat, which required read-write-modifying corrupted data).
Generally, these devices have ECC granularity <= the bus width. In
those cases, if you send a PutFull, the first beat carries the
error value for the whole burst. Consider:
If the PutFull was below the granularity, it was a single beat.
If the PutFull was multi-beat, it exceeds the granularity.
Therefore, an important variation on the earlyAck optimization is
the case where only PutFulls receive an earlyAck.
2017-11-08 15:31:19 -08:00
Palmer Dabbelt
8700728a35
Bump riscv-tools, for a new toolchain release
2017-11-08 14:26:55 -08:00
Andrew Waterman
4514adb77c
Merge pull request #1093 from freechipsproject/local-error-interrupt
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generate local interrupts on bus/ecc errors
2017-11-07 14:19:53 -08:00
Henry Cook
d096fd206b
coreplex: WithStatelessBridge => WithIncoherentTiles ( #1092 )
2017-11-07 13:47:56 -08:00
Andrew Waterman
34f38b0fb1
Don't permit vectoring of high interrupts
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Send them to the base of the vector to obviate an adder
2017-11-07 01:59:30 -08:00
Andrew Waterman
6176b348dc
Invalidate TL error bit in D$ once progress is made
2017-11-07 00:52:18 -08:00
Andrew Waterman
d8d4504995
Provide separate masks for local & global BusErrorUnit interrupts
2017-11-06 18:03:59 -08:00
Andrew Waterman
be3a3e0187
Generate local interrupt #128 on bus errors
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It doesn't have a correpsonding bit in mip/mie, so it isn't individually
maskable, nor is it delegable.
2017-11-06 18:03:59 -08:00
Andrew Waterman
ac096a89e7
Make BusErrorUnit support 32-bit stores
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Otherwise it isn't too useful for RV32!
2017-11-06 18:03:59 -08:00
Andrew Waterman
6357db0b12
Expose BusErrorUnit non-diplomatically for use as local interrupt
2017-11-06 18:03:59 -08:00
Andrew Waterman
bdda2cb145
Merge pull request #1089 from freechipsproject/aswaterman-patch-1
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Don't emit PTW covers when !usingVM
2017-11-06 18:03:36 -08:00
Wesley W. Terpstra
1f5fb5d643
Merge pull request #1091 from freechipsproject/atomic-automata-errors
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tilelink: AtomicAutomata should OR the Get error with the Put error
2017-11-06 13:58:02 -08:00
Andrew Waterman
95d00b13cc
Report ITIM slave port errors to BusErrorUnit
2017-11-06 12:39:17 -08:00
Andrew Waterman
c84848afa6
Report ITIM uncorrectable errors over D-channel
2017-11-06 12:32:45 -08:00
Wesley W. Terpstra
7cc7cd5992
tilelink: AtomicAutomata; add errors to the unit test
2017-11-06 12:05:44 -08:00
Wesley W. Terpstra
88234ead0d
tilelink: generalize ErrorEvaluator to more than just address patterns
2017-11-06 11:53:09 -08:00
Wesley W. Terpstra
25ea7fa852
tilelink: AtomicAutomata should OR the Get error with the Put error
2017-11-06 11:31:23 -08:00
Wesley W. Terpstra
dcf67b49fa
BusBypass: only stall A once the last beat is accepted ( #1090 )
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When switching ports, the bypass stalls new messages until all
outstanding messages have received their responses. However, this
stall must NOT stop the remaining beats of a partially sent request.
2017-11-06 11:13:15 -08:00
Andrew Waterman
989eeb78f9
Prevent some unnecessary pipeline replays
2017-11-06 11:04:06 -08:00
Andrew Waterman
c8bc487ab8
Use pseudo-LRU policy in BTB
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FIFO falls on its face if the working set doesn't fit in the BTB.
2017-11-03 16:27:04 -07:00
Andrew Waterman
f859da85ff
Disable covers that don't apply to DTIM
2017-11-03 15:38:13 -07:00
Andrew Waterman
d6ede818ee
DTIM doesn't accept grants
2017-11-03 15:37:48 -07:00
