riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,534 Commits 1 Branch 0 Tags 13 MiB
f61e30763f
Commit Graph

4534 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Jack Koenig
288d7169ae Bump firrtl and update vsim Makefrag-verilog (#409) 2016-10-23 23:07:47 -07:00
Wesley W. Terpstra
8bfd6bcd4d axi4: ensure we accept AR before reporting R (#411) 2016-10-21 21:02:05 -07:00
Colin Schmidt
cb8878c931 Don't build any hurricane branches 
Don't mean to eat up travis bandwidth but shared branches sometimes get made.
 2016-10-21 16:26:41 -07:00
Colin Schmidt
85f3788ab5 initialize s2_hit to solve #401 2016-10-21 14:53:55 -07:00
Scott Johnson
a919a280e8 Fix Cadence Incisive compile errors; VCD-Plus is a VCS-only format 
This fixes the following compile warnings and simulation errors:

Compile-time warnings:
      $vcdplusfile(vcdplusfile);
                 |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): Unrecognized system task or function: $vcdplusfile (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
      $vcdpluson(0);
               |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): Unrecognized system task or function: $vcdpluson (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
      $vcdplusmemon(0);
                  |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): Unrecognized system task or function: $vcdplusmemon (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
        `VCDPLUSCLOSE
                    |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): Unrecognized system task or function: $vcdplusclose (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].

Which then become simulation-time errors:

      $vcdplusfile(vcdplusfile);
                 |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): User Defined system task or function ($vcdplusfile) registered during elaboration and used within the simulation has not been registered during simulation.
      $vcdpluson(0);
               |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): User Defined system task or function ($vcdpluson) registered during elaboration and used within the simulation has not been registered during simulation.
      $vcdplusmemon(0);
                  |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): User Defined system task or function ($vcdplusmemon) registered during elaboration and used within the simulation has not been registered during simulation.
        `VCDPLUSCLOSE
                    |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
        `VCDPLUSCLOSE
                    |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,97|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
 2016-10-19 13:26:31 -07:00
Scott Johnson
9f0fda01b3 Fix Cadence Incisive compile warning 
The SystemVerilog LRM (IEEE 1800-2012) clause 20.15.1 ($random
function) says: "The seed argument shall be an integral variable."

This fixes the following compile warning:

    rand_value = $random($urandom);
                       |
ncelab: *W,WRNOTL (/home/scottj/rocket-chip/vsrc/TestDriver.v,34|23): Argument to out parameter is not a legal lvalue.
 2016-10-19 13:23:36 -07:00
Scott Johnson
f069052969 Merge pull request #403 from ucb-bar/fix-incisive-warning 
Fix Verilog compile warning from Cadence Incisive
 2016-10-18 10:48:32 -07:00
Scott Johnson
dc4c375c7f Silence Verilog compile warning from Cadence Incisive 2016-10-17 15:44:24 -07:00
Wesley W. Terpstra
c8fc05d154 Merge pull request #402 from ucb-bar/axi4-slave 
AXI4=>TL2 converter
 2016-10-17 10:34:29 -07:00
Wesley W. Terpstra
7c334e3c34 axi4 ToTL: shorter critical path on Q.bits if errors go first 2016-10-17 01:00:49 -07:00
Wesley W. Terpstra
73010c79a3 axi4 ToTL: handle bad AXI addresses 2016-10-17 00:12:26 -07:00
Wesley W. Terpstra
501d6d689f axi4: Test ToTL 2016-10-16 22:04:06 -07:00
Wesley W. Terpstra
5a1da63b5a axi4: prototype ToTL adapter 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
72e5a97d40 tilelink2: factor out the OH1ToOH function 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
d09f43c32f axi4 Bundles: add a size calculation helper 
The old version was wrong.
Inverting before the << has a different width.
This means you end up with high bits set.
 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
ee66fd28eb Merge pull request #400 from ucb-bar/better-crossing-asserts 
Better crossing reset handling
 2016-10-14 19:19:37 -07:00
Wesley W. Terpstra
20288729b9 tilelink2 Isolation: cross the valid signals as well 
Refactor the code to be less copy-pasty
 2016-10-14 18:28:36 -07:00
Wesley W. Terpstra
680a944f07 regmapper RegisterCrossing: safe AsyncQueues are overkill here 2016-10-14 18:28:31 -07:00
Wesley W. Terpstra
ac0bb841da AsyncQueue: cope with far reset propagation delay 2016-10-14 18:05:35 -07:00
Wesley W. Terpstra
8f3c2ddfc3 tilelink2 Crossing: these asserts should be done by the AsyncQueue 2016-10-14 16:54:09 -07:00
Wesley W. Terpstra
a82cfb8306 tilelink2: replace addr_hi with address (#397) 
When faced with ambiguous routing of wmask=0, we decided to include
all the address bits. Hopefully in most cases the low bits will be
optimized away anyway.
 2016-10-14 14:09:39 -07:00
Wesley W. Terpstra
9655621aa8 Merge pull request #396 from ucb-bar/decoupled 
TL2 Decoupled
 2016-10-13 19:09:58 -07:00
Wesley W. Terpstra
4e40f9bb59 tilelink2 Nodes: appease the PC police 2016-10-13 17:02:18 -07:00
Wesley W. Terpstra
54b73aef57 tilelink2: WidthWidget and Fragmenter no longer erase latency 2016-10-13 17:02:18 -07:00
Wesley W. Terpstra
200cf3dd13 tilelink2 Nodes: include some options to test for conformance 2016-10-13 17:02:18 -07:00
Wesley W. Terpstra
5d5b5a66f4 tilelink2 RAMModel: fix a write-bad-data bug 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
e5a1483358 tilelink2 Fragmenter: eliminate most of the registers on A 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
99c7003d11 tilelink2: allow preemption of Fragmenter and WidthWidget 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
b42cfdc9dd tilelink2 Arbiter: there is only one winner 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
b6e9b0c558 tilelink2 Arbiter: allow preemption of first beat 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
0aebf9e341 tilelink2 ToAXI4: no arbitration path register needed 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
0e897b905f tilelink2 RegisterRouter: data path register is no longer required 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
c4eadd3ab3 tilelink2 Monitor: enforce stricter transaction ordering 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
d8a1163131 tilelink2 Monitor: don't enforce Irrevocable any more 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
405f66da32 tilelink2 WidthWidget: cope with Decoupled inputs 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
e2e72ac979 tilelink2 Fragmenter: cope with Decoupled input 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
023c6402e9 tilelink2: switch to DecoupledIO syntax 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
980bb3fbfd Merge pull request #395 from ucb-bar/axi4-fragmenter 
AXI4 fragmenter
 2016-10-13 17:01:53 -07:00
Wesley W. Terpstra
4c1c52486b axi4 Fragmenter: handle more inflight AXI requests than we have space 2016-10-13 15:52:32 -07:00
Wesley W. Terpstra
8005266131 axi4 Fragmenter: refine sideband FSM for case of last fragment 2016-10-13 15:52:32 -07:00
Wesley W. Terpstra
19064e602b axi4 Fragmenter: align all output accesses 
We promised the output is aligned. Make good on that!
 2016-10-13 15:52:27 -07:00
Wesley W. Terpstra
84be93f9f3 axi4 Fragmenter: confirm correct handling of last 2016-10-13 14:01:23 -07:00
Wesley W. Terpstra
1c79a23a8b axi4 Fragmenter: initialize error response to 0 2016-10-13 13:46:24 -07:00
Wesley W. Terpstra
958af132ba axi4 Fragmenter: optimize dynamic slave lookup 2016-10-12 17:29:38 -07:00
Wesley W. Terpstra
11169d155c axi4: add a Buffer to put between nodes 2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
a9a3f7dd4e tilelink2 RAMModel: include name of test in output 2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
345eefd81b axi4: include unit tests 2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
a6c6d99848 axi4: prototype Fragmenter 2016-10-12 17:08:49 -07:00
Wesley W. Terpstra
c918aa6d89 axi4: name AdapterNode parameters properly 2016-10-12 17:02:02 -07:00
Wesley W. Terpstra
a423f97844 axi4: parameterized AXI master constraint for aligned access 2016-10-12 17:02:02 -07:00