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Commit Graph

2249 Commits

Author SHA1 Message Date
d9c5ec4f7b coreplex: HasTiles supplies def tileParams 2017-12-20 17:18:55 -08:00
ddaeedf2d0 coreplex: make HasTiles more generic
HasTiles now deals with only extremely general tile IOs.
Some RocketTiles specific behavior moved into RocketCoreplex.
BaseTile now has optional LocalInterruptNode.
2017-12-20 17:18:55 -08:00
895c4b9261 Revert "ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144)" (#1162)
This reverts commit a542ae687e.
2017-12-19 12:16:26 -08:00
74d9326ebc JTAG: Revert to Chisel._ for Issue 1160 (#1161)
* JTAG: Revert to Chisel._ for Issue 1160

* JTAG: Revert to Chisel._ for Issue 1160

* jtag: revert everything to Chisel._

* jtag: Revert all modules to Chisel._ vs chisel3, due to FIRRTL issues with chisel3 generated code
2017-12-18 21:02:31 -08:00
a31ba2ea2e diplomacy: LazyModule factory uses ValName (#1159)
* diplomacy: LazyModule factory uses ValName
2017-12-18 15:40:30 -08:00
09160d0cd5 Changed label for DCache and ICache error covers + take away exclusio… (#1155)
* Changed label for DCache and ICache error covers + take away exclusion that shouldn't be there

* rocket: add d-channel error to I$
2017-12-13 20:16:36 -08:00
a542ae687e ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144) 2017-12-08 17:35:14 -08:00
c2a0319dc4 Merge pull request #1151 from freechipsproject/error-atoms
Error atomics
2017-12-08 17:34:55 -08:00
efc793d52e CloneModule: must be public to be used in pattern matches 2017-12-08 14:57:08 -08:00
2ca03384ec diplomacy: skip anonymous class names 2017-12-08 14:36:12 -08:00
588dacec17 Bump Chisel and Firrtl (#1134) 2017-12-08 14:22:18 -08:00
18b8a61775 Error device: require explicit control of atomic and transfer sizes 2017-12-08 13:41:09 -08:00
6a0150aad7 Error device: mark executable to support testing erroneous I$ refill 2017-12-08 12:38:06 -08:00
676110bc1f Add cover for a1ebe6da4d 2017-12-07 21:03:42 -08:00
a1ebe6da4d Prevent frontend deadlock fetching from uncacheable memory
After detecting a corrupted BTB, don't speculatively update it until
the next non-speculative fetch.  This prevents the frontend from replaying
forever.
2017-12-07 18:56:06 -08:00
ec3789b365 Add Cross Cover Property Library (#1149)
Add cover points related to memory error to I/D Cache
2017-12-07 18:46:10 -08:00
5c204f98d5 When writing full words to ITIM, ECC errors are correctable (#1148)
* When writing full words to ITIM, ECC errors are correctable

* Disable D$ tag reset state machine when using scratchpad
2017-12-07 16:00:26 -08:00
50de991f18 Fix typo in breakpoint cover property. 2017-12-04 14:04:24 -08:00
b8098d18be diplomacy: remove the :=? operator in favour of magic :*=* (#1139)
The reason for the :=? operator was for when you have an adapter chain
whose direction of cardinality you could not know. We used explicit
directives to tell these compositions which way to go.

Unfortunately, that makes the API leaky. You think the chain of adapters
is just one adapter, but you have to use strange Cardinality scopes to
use it. That's just bad.

The new :*=* just automagically figures it out from the graph.
2017-12-01 18:28:37 -08:00
dedf396915 groundtest: connect the ibus to a fictitious master (#1140) 2017-12-01 18:28:24 -08:00
71ddd797bf Merge pull request #1138 from freechipsproject/cover_tag_ecc_error_during_fence_i
Added coverage point to cover the case when ECC error happens during …
2017-12-01 18:00:11 -08:00
7c2df9f0bf Cover the case when there is an ECC error in DCache data array during fence.i execution 2017-12-01 16:28:28 -08:00
74bd61c556 Added coverage point to cover the case when ECC error happens during fence.i execution 2017-12-01 15:50:31 -08:00
8781d2b2e7 diplomacy: provide a val name for all LazyModule constructions 2017-12-01 11:28:21 -08:00
fe8d557751 PeripheryBus: automatically disappear when not used 2017-12-01 11:26:59 -08:00
93c8010aca FrontBus: automatically disappear when not used 2017-12-01 11:26:59 -08:00
e489c4226e diplomacy: remove node arity and allow empty Nexus nodes (Xbars)
This removes the mostly obsolete 'numIn/Out' range restrictions on nodes.
It also makes it possible to connect optional crossbars that disappear.

val x = TLXbar()
x := master
slave := x

val y = TLXbar()
x :=* y // only connect y if it gets used

This will create crossbar x, but crossbar y will disappear.
2017-12-01 11:26:59 -08:00
6a25a3b7ac tilelink: we can have helper objects for terminal nodes now too!
The new rule is you should have an object.apply method if you only have a
single .node.
2017-12-01 11:26:59 -08:00
2092cb4ec8 diplomacy: reprotect Node bundles after module construction is completed 2017-12-01 11:26:59 -08:00
fdeed7bbb3 unittest: add an API for describing LazyModule unit tests 2017-12-01 11:26:59 -08:00
cc789e9063 diplomacy: protect more of the unstable API 2017-12-01 11:26:59 -08:00
8ed9e78903 diplomacy: support cloning of LazyModules 2017-12-01 11:26:59 -08:00
b43bcdfcd1 CloneModule: beat chisel into submission 2017-12-01 11:26:59 -08:00
1f23f9f865 diplomacy: categorize parameter resolution by direction+side 2017-12-01 11:26:59 -08:00
fbbfc9c096 diplomacy: include edge type in inward/outward node handles
This is necessary capture the node implementation in the handle,
which is in turn necessary to support cloning a Node.
2017-12-01 11:26:58 -08:00
35506279af regmapper: fix d_ready => d_bits loop in RegField.bytes
RegField.bytes updates only those bytes which are written every cycle.
However, there was a bug that it would try to return the updated value on reads.
This led to another TL-spec violating combinational path, just like the Debug module.
2017-11-30 16:38:45 -08:00
fc1f5be316 Debug: fix a latent combinational loop (d_ready => d_bits)
When passed a Wire, WNotify outputs that wire on reads wire => d_bits.
Furthermore, it updates the Wire when a write occures d_ready => wire.

These registers should be returning undefined value on read, anyway.
2017-11-30 16:36:45 -08:00
a447343074 Merge pull request #1129 from freechipsproject/add-exception-cover-properties
Add cover properties for exceptions in the core.
2017-11-30 16:23:14 -08:00
4bd9c477ea Add cover properties for ECALL exceptions. 2017-11-30 14:27:04 -08:00
29c70501f2 Add cover properties for exceptions in the core. 2017-11-30 14:27:04 -08:00
890528c641 Avoid data corruption under correctable tag error during flush
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
2017-11-29 16:09:44 -08:00
34d86ef665 Revert "Avoid data corruption under correctable tag error during flush (#1130)"
This reverts commit 44eb4d12b5.
2017-11-29 16:09:30 -08:00
44eb4d12b5 Avoid data corruption under correctable tag error during flush (#1130)
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
2017-11-29 09:42:00 -08:00
f554ad7e2c debug: Remove workaround for Chisel 3 #527 2017-11-27 10:50:15 -08:00
5155eb6059 Don't emit writeback state machine logic for scratchpad (#1127)
Firrtl can't DCE it because it would require analyzing the state machine.
2017-11-22 18:40:02 -06:00
6f3ff634f2 DTS: collect common DTS nodes and move timebase-frequency to cores
Putting the common DTS nodes into a shared object makes them get
emitted only one time. Plus it's better style.

timebase-frequency should really have been in the cpu nodes in the
first place according to the spec anyway. I was foolishly trying to
save bytes. However, now we really want it there in case it differs.
2017-11-20 18:09:57 -08:00
3b299397db diplomacy: bind resources to outer-most binding
This is probably the wrong thing to do, but it is expedient for now.
We need a better way to do cross-coreplex visibility.
2017-11-20 17:42:08 -08:00
44f99cd9a5 diplomacy: eliminate redundant bindings 2017-11-20 17:42:08 -08:00
baa31edf7d RocketTile: if the dcache is incoherent, report it in DTS 2017-11-20 17:42:06 -08:00
a60d7d419d icache: add a couple cover points for I$ and ITIM iteraction 2017-11-20 13:14:38 -08:00