riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,289 Commits 1 Branch 0 Tags 13 MiB
eef05cc1fc
Commit Graph

4289 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
roman3017
2979badf75 Update README.md 
Fixed path to Configs.scala
 2016-09-12 18:55:14 -07:00
Wesley W. Terpstra
273d3a73f2 tilelink2: Unit Test passes! 2016-09-12 18:39:50 -07:00
Colin Schmidt
a10d058e1a fix warnings in verilog source (#274) 2016-09-12 18:25:35 -07:00
Wesley W. Terpstra
9874bc553a tilelink2: Fragmenter supports Hints 2016-09-12 17:31:59 -07:00
Wesley W. Terpstra
42955a0490 tilelink2: HintHandler optimize to nothing if unneeded 2016-09-12 17:31:16 -07:00
Wesley W. Terpstra
94761f714d tilelink2 HintHandler: fill in correct sink in responses 2016-09-12 17:26:40 -07:00
Wesley W. Terpstra
ca5f98f138 tilelink2: Hints are not special 
Hints have a TransferSize limit just like all other message types.
 2016-09-12 17:15:28 -07:00
Henry Cook
ad8e563c89 [tilelink2] Fuzzer: Rewrite of fuzzer 
Multiple bug-fixes and actual source id generation.
 2016-09-12 17:00:58 -07:00
Henry Cook
0b0c891179 [tilelink2] Monitor: Allow zero-mask PutPartials 
this will require a larger address refactoring TBD
 2016-09-12 17:00:50 -07:00
Henry Cook
c57b52ec86 tilelink2 Fragmenter: bugfix using D.hasData 2016-09-12 16:58:21 -07:00
Henry Cook
82681179cb [tilelink2] Edges: add size to addr_lo. 
addr_lo cannot correctly be deciphered from the mask alone.
OxC still has addr_lo === 0 if size is >1.
 2016-09-12 16:58:09 -07:00
Andrew Waterman
88440ebf89 Use PseudoLRU in BTB when possible (for powers of two) 2016-09-12 16:52:03 -07:00
Andrew Waterman
266a2f24bd Disable Mul early out by default if XLen == 32 
With a default unroll of 8, it doesn't help performance, but costs area.
 2016-09-12 16:50:08 -07:00
Andrew Waterman
96185e4b16 tighten an assert condition 
dcache.s1_kill is a don't-care if dcache.req.valid wasn't previously high
 2016-09-12 16:49:46 -07:00
Andrew Waterman
beb141a20b Allow M, A, D, C extensions to be disabled in misa register 2016-09-12 16:49:46 -07:00
Andrew Waterman
e66abb5e92 Merge pull request #276 from ucb-bar/nmemchannels-fix 
Pass nMemChannels to coreplex through CoreplexConfig
 2016-09-12 14:05:50 -07:00
Howard Mao
f3cdeb08c6 pass nMemChannels to coreplex through CoreplexConfig 2016-09-12 12:40:10 -07:00
Howard Mao
9d9f90646d allow configuration of simulation memory latency 2016-09-12 12:33:50 -07:00
Andrew Waterman
49bba961cf Merge pull request #259 from ucb-bar/refactor-periphery 
Refactor Periphery
 2016-09-12 12:18:00 -07:00
Henry Cook
a21b04a7c1 playground for making different DAGs to use as DUTs 2016-09-12 10:32:45 -07:00
Henry Cook
0671d5d637 Initial version of fuzzer and simple ram fuzz test 2016-09-12 10:32:45 -07:00
Wesley W. Terpstra
7760459b76 tilelink2 RegisterRouter: add RegField test patterns 2016-09-12 10:32:25 -07:00
Wesley W. Terpstra
85ae77c108 tilelink2 RAMModule: carefully stage the pipeline to make BRAMs possible 2016-09-12 10:32:25 -07:00
Wesley W. Terpstra
9560df537c tilelink2 RegisterRouter: allow sub-4k devices in order to make useful unit tests 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
26f9e2dfbd tilelink2 Parameters: fix width=1 address truncation bug 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
98a4facac7 tilelink2 RAMModel: clear Mems on power-up 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
17f7ab18de tilelink2 RAMModel: model the state a RAM would have for Put+Gets 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
488b93d146 tilelink2 Parameters: if you support PutPartial, you must support PutFull 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
d6261e8ce8 tilelink2 Edge: add a numBeats1 method for predecremented code 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
5604049927 tilelink2 Buffer: support an unlimited number of channels 2016-09-12 10:32:24 -07:00
Yunsup Lee
d985cdfc66 Merge branch 'master' into refactor-periphery 2016-09-10 23:42:13 -07:00
Yunsup Lee
fea31c7061 let GlobalAddrMap and ConfigString overridable 2016-09-10 23:39:44 -07:00
Yunsup Lee
bb3f514e8d now able to add periphery devices through traits 
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
 2016-09-10 23:39:29 -07:00
mwachs5
395bc16da6 Merge pull request #271 from ucb-bar/black_box_regs_fix 
Get rid of the unecessary Parameters for Async Reset Reg
 2016-09-10 14:14:12 -07:00
Megan Wachs
77e4aa63f8 Get rid of the unecessary Parameters for Async Reset Reg 2016-09-09 16:24:35 -07:00
Andrew Waterman
e6889ea711 Merge pull request #269 from ucb-bar/tweaks 
Two tweaks to Rocket perf & QoR
 2016-09-09 15:25:15 -07:00
Andrew Waterman
b695ab5292 Merge branch 'master' into tweaks 2016-09-09 15:04:21 -07:00
mwachs5
8273ca1ae7 Merge pull request #265 from ucb-bar/black_box_regs 
Make it possible to have Async Reset Flops
 2016-09-09 13:54:04 -07:00
Megan Wachs
5f5989848c Merge remote-tracking branch 'origin/master' into black_box_regs 2016-09-09 13:12:52 -07:00
Colin Schmidt
cf3c6fa277 add STOP_COND to emulator & match vsim PRINTF_COND 2016-09-09 11:07:17 -07:00
Andrew Waterman
656aa78f7d Pipeline FMAs more deeply by default 
Rocket's QoR has improved enough that the FMAs are on the critical
path.  This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
 2016-09-09 11:06:42 -07:00
Andrew Waterman
eaa4b04ee5 Check D$ store->load collisions more precisely 
Tolerate, for example, a half-word store and a half-word load to
different halves of the same word.
 2016-09-09 11:06:42 -07:00
Henry Cook
c4593d2034 Merge pull request #266 from ucb-bar/multinode 
TL2Node: make it possible for {Identity,Output,Input}Node to pass a Vec
 2016-09-09 10:17:45 -07:00
Wesley W. Terpstra
c28ca37944 tilelink2: get rid of fragile implicit lazyModule pattern, and support := 
We can more reliably find the current LazyModule from the LazyModule.stack
 2016-09-08 23:06:59 -07:00
Wesley W. Terpstra
b587a409a3 tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec 
In order to implement a pass-through RAM Monitor model, we will want to support
a variable number of inputs and outputs with BOTH different manager and client
parameters on each bundle.
 2016-09-08 21:34:20 -07:00
Yunsup Lee
176f385b1d Merge pull request #263 from ucb-bar/intbar 
TL2 Interrupts
 2016-09-08 21:33:25 -07:00
Wesley W. Terpstra
48ca478578 Merge branch 'master' into intbar 2016-09-08 21:09:59 -07:00
Wesley W. Terpstra
808a7f60f4 tilelink2 Legacy: it's only an error if it's valid (#264) 2016-09-08 21:09:40 -07:00
Megan Wachs
fda4c2bd76 Add a way to create Async Reset Registers and a way to easily access them with TL2 2016-09-08 20:02:07 -07:00
Megan Wachs
c1eb1f12a2 tilelink2: Rename GPIO to Example to avoid conflicts with real GPIO devices 2016-09-08 20:02:07 -07:00