riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
3,147 Commits 1 Branch 0 Tags
edb17d1e342f7fecfc9efeccfe5ff5ef1538ff5b
Commit Graph

3147 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Andrew Waterman
5644a2703a Avoid need for FENCE.I in debug programs 
This is a hack to work around caching the (uncacheable) debug RAM.  The
RAM is always entered with a JALR, so flush the I$ on any debug-mode JALR.
 2016-06-23 00:01:06 -07:00
Andrew Waterman
7f88a00a38 Always verify BTB result; don't bother flushing it 
This improves CPI for things like

    lbu t0, (t0)
    j foo
    addi t0, t0, 1

where the addi would stall, causing j's misprediction check to fail,
flushing the pipeline.
 2016-06-23 00:01:06 -07:00
Howard Mao
255ef05e21 bump rocket 2016-06-22 17:59:05 -07:00
Howard Mao
338f959620 get rid of commented out code 2016-06-22 17:36:53 -07:00
Howard Mao
4fbe7d6cf7 split the isa tests properly 2016-06-22 16:14:02 -07:00
Howard Mao
4c31248917 make sure UseAtomics is on when PTW is being used 2016-06-22 16:09:45 -07:00
Howard Mao
5edb448a1f get rid of slow DualCoreConfig in Travis for now 2016-06-22 16:09:14 -07:00
Howard Mao
3c973d429a rename SmallConfig to WithSmallCores 2016-06-22 16:08:27 -07:00
Howard Mao
9b9ddd0d54 get rid of leftover backup memory code 2016-06-22 16:06:41 -07:00
Howard Mao
e3d3b2264a fix MuxCase and MuxLookup 2016-06-21 14:03:10 -07:00
Howard Mao
0967f3cfed use MuxCase and MuxLookup instead of MuxBundle 2016-06-21 14:01:23 -07:00
Howard Mao
e3391b36b2 get rid of MuxBundle now that MuxCase and MuxLookup are fixed 2016-06-21 10:43:44 -07:00
Howard Mao
ff43238e6e give DualCoreConfig L2 cache to speed up test runs 2016-06-20 17:58:26 -07:00
Howard Mao
daa0f3038f invoke firrtl jar directly in order to control heap memory usage 2016-06-20 13:02:31 -07:00
Howard Mao
82169e971e Dynamically compute number of L1 client channels 
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.

This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
 2016-06-20 13:02:31 -07:00
Howard Mao
d1c83ccda0 change Tile interface to allow arbitrary number of cached and uncached channels 2016-06-20 09:55:30 -07:00
Andrew Waterman
4a8e6c773a Fix +verbose flag for verilator 2016-06-17 21:09:08 -07:00
Andrew Waterman
60bddddfe6 Merge sptbr and sasid 2016-06-17 18:29:05 -07:00
Howard Mao
719fffff40 make sure updates from irel and iacq gated by tracker allocation 2016-06-17 17:15:02 -07:00
Howard Mao
b75b6fdcda make sure no-data voluntary releases get tracked 2016-06-17 17:15:02 -07:00
Howard Mao
ebe95fa827 fix wmask buffer clearing in L2 agents 2016-06-16 15:34:31 -07:00
Howard Mao
aba13cee7f fix BRAM slave so that it can correctly take all TileLink requests 2016-06-16 15:34:31 -07:00
Howard Mao
e716661637 make sure merged no-alloc put still allocs if original put allocs 2016-06-16 15:34:31 -07:00
Howard Mao
7e43b1d889 fix mistaken dequeueing from roq in TileLink unwrapper 2016-06-16 15:34:31 -07:00
Howard Mao
2789e60b6b fix ignt_q logic 2016-06-16 15:18:58 -07:00
Henry Cook
16bfbda3c9 Refactor the TransactionTracker logic in all the L2 TileLink Managers. 
They now share common sub-transactions within traits, and use a common
set of state transitions and scoreboarding logic. Tracker allocation
logic has also been updated. No changes to external IOs or the TileLink protocol.
A new bufferless Broadcast hub is also included, but does not yet pass fuzzing checks.
 2016-06-16 15:18:48 -07:00
Howard Mao
181b11bf20 allow Comparator to disable prefetches (for testing BroadcastHub) 2016-06-16 15:14:02 -07:00
Howard Mao
a43a93b55c add BRAMSlave unittest 2016-06-16 15:13:40 -07:00
Palmer Dabbelt
25ade44fe3 Don't build the Verilator man pages (#141) 
These failed for Andrew earlier.  While it might be paranioa, there's
really no reason to build the man pages so we might as well not bother.
 2016-06-16 10:13:21 -07:00
Colin Schmidt
ba35712f08 Merge pull request #140 from ucb-bar/verilator 
Default to Chisel 3
 2016-06-15 16:25:07 -07:00
Andrew Waterman
0b4c8e9af7 Add D-mode single-step support 2016-06-15 16:21:24 -07:00
mwachs5
2d2096e509 Add smaller ROM/RAM for 32-bit debug (#60) 2016-06-15 15:07:43 -07:00
Palmer Dabbelt
68ba33369b Default to Chisel 3 
Now that we can test Chisel 3 on Travis, I think it's time to turn it on
for everyone else.
 2016-06-15 14:01:43 -07:00
Palmer Dabbelt
e617bb8aa8 Start testing Chisel 3 in Travis 
Now that we have verilator support we can start testing the Chisel 3
Verilog on Travis.  This disables Chisel 2 Travis tests because they're
too slow.
 2016-06-15 14:01:22 -07:00
Palmer Dabbelt
f6432395cb Allow the regressions to run more than once 2016-06-14 21:21:44 -07:00
Palmer Dabbelt
1525b4717e Install Verilator when building the emulator 
We need a fairly new version of Verilator, so I just added a rule to
download and install it on all systems.
 2016-06-14 21:21:43 -07:00
Colin Schmidt
1c2c9f8ed1 bump rocket to fix RoccExampleConfig 2016-06-14 21:21:06 -07:00
Howard Mao
377de06b72 fix comparator Chisel2 compilation issue 2016-06-14 18:36:38 -07:00
Howard Mao
b7c0d0cb4d test both cached and uncached cases in MixedAllocPutRegression 2016-06-14 17:32:29 -07:00
Colin Schmidt
e3816d5fc7 set invalidate_lr in other rocc examples (#47) 
This should fix https://travis-ci.org/ucb-bar/rocket-chip/jobs/137607305
 2016-06-14 16:59:37 -07:00
Palmer Dabbelt
571b5b2093 Prevent sbt from running multiple times in emulator 
If you have multi-target rules that don't have %s in them, make
interprets that as "run this recipe multiple times, once to produce each
target".  If you have %s in the rules, then make interprets it as "run
this recipe once to produce all targets".  We want the second one.
 2016-06-14 11:59:20 -07:00
Yunsup Lee
3ce8dbb6e5 fix make error mixing implicit and normal rules 2016-06-14 11:59:20 -07:00
Howard Mao
1074c9fe6d change the way regression IOs are assigned 2016-06-14 11:06:45 -07:00
Howard Mao
e284257052 fully disable the cache when not using it in regression tests 2016-06-14 11:06:45 -07:00
Howard Mao
3e105eb352 make sure MixedAllocPutRegression uses a block that hasn't been cached already 2016-06-13 18:17:48 -07:00
Howard Mao
fe8d81958f fix groundtests to fit new way of parameterizing TileLink clients 2016-06-13 16:17:27 -07:00
Howard Mao
a921458758 add a regression test for no-alloc Put following an alloc Put 2016-06-13 16:17:27 -07:00
Andrew Waterman
e3b4b55836 Refactor breakpoints and support range comparison (currently disabled) 2016-06-10 19:55:58 -07:00
Palmer Dabbelt
82cef6fa7b Make a TileLink to Smi converter availiable to users (#136) 
See the cooresponding uncore commit for details.
 2016-06-10 18:49:17 -07:00
Palmer Dabbelt
0c695d8e83 Use the new TileLink to Smi converter (#10) 
I pulled out the TileLink to Smi converter and put it in uncore so I can
use it for my own stuff.
 2016-06-10 14:04:48 -07:00