Wesley W. Terpstra
7971947d6c
tilelink2 Monitor: don't inspect bits if valid is forbidden
2017-03-19 16:34:23 -07:00
Wesley W. Terpstra
a4ca424a22
AHBToTL: finally get the error signal right? ( #594 )
2017-03-18 22:24:20 -07:00
Wesley W. Terpstra
f6daa782d3
AHBToTL: fix the order of updates to d_pause ( #592 )
2017-03-17 19:34:40 -07:00
Megan Wachs
dcc9827ab4
Rename Prci.scala to Clint.scala ( #591 )
...
The internals of this were renamed to CoreplexLocalInterrupter, so changing the top level name to match.
2017-03-17 15:36:10 -07:00
Wesley W. Terpstra
db55a1d755
Fragmenter: fix a bug when underlying device supports larger bursts ( #589 )
2017-03-17 11:00:49 -07:00
Wesley W. Terpstra
9b5b3279a6
AHBToTL: don't report error during idle cycles
2017-03-16 18:18:29 -07:00
Wesley W. Terpstra
5efd38bf97
apb: put both aFlow options under regression
2017-03-16 15:36:14 -07:00
Wesley W. Terpstra
882a7ff8ff
TLToAPB: use the now standard aFlow parameter name
2017-03-16 15:34:59 -07:00
Wesley W. Terpstra
e31b84af33
axi4: use common BufferParams
2017-03-16 15:32:17 -07:00
Wesley W. Terpstra
ca2c709d29
TLBuffer: move TLBufferParams to diplomacy.BufferParams
2017-03-16 15:19:36 -07:00
Wesley W. Terpstra
778c8a5c97
ToAHB: appease AHB VIP
2017-03-16 15:17:05 -07:00
Wesley W. Terpstra
963d244094
unittest: try both aFlow settings of TLToAHB
2017-03-16 15:13:57 -07:00
Wesley W. Terpstra
604a164b97
TLToAHB: rename parameter to aFlow
2017-03-16 15:10:54 -07:00
Wesley W. Terpstra
bb49575368
ahb: rewrote TLToAHB to avoid retracting requests on stall
2017-03-16 14:36:30 -07:00
Wesley W. Terpstra
c95c2ca9c8
AHB: include bridge unit tests
2017-03-14 18:34:21 -07:00
Wesley W. Terpstra
0c5fd76089
ahb: implement a ToTL bridge
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
7f71df0925
apb: better test coverage
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
5885bf29b5
axi4: improve test harness
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
d98fd942f1
tilelink2: optimize the supportsX check circuits
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
3c5c877409
tilelink2: make TLBuffer API more flexible
2017-03-14 14:06:18 -07:00
Wesley W. Terpstra
6fc3ec3d63
tileink2: add a TestRAM; a zero-delay RAM useful for testing
...
TLRAM always answers after 1 cycle. We need a RAM that answers in 0.
2017-03-14 14:06:17 -07:00
Henry Cook
bb0390630c
Merge branch 'master' into priv-1.10
2017-03-13 21:40:12 -07:00
Wesley W. Terpstra
eaf474a081
LFSR: use random intial value of the start register
...
We just need to make sure it doesn't initialize randomly stuck at 0.
2017-03-13 13:17:52 -07:00
Henry Cook
1a3fec61c0
Merge branch 'master' into priv-1.10
2017-03-13 11:59:18 -07:00
Wesley W. Terpstra
d2da33e4b1
Fuzzer: use different LFSR seeds based on simulator seed
2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
bb6108abd5
Tests: include more random delays
2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
0c7fb87390
TLDelayer: insert noise on invalid cycles
2017-03-11 02:53:43 -08:00
Jacob Chang
1c6dde8c15
Make parameters for TLToAHB and TLToAXI4 accessable ( #581 )
2017-03-10 22:26:38 -08:00
Henry Cook
dbc8f4b30b
last => done
2017-03-10 15:58:38 -08:00
Andrew Waterman
33b6d48376
Fix haltnot reporting (previously always returned 0)
2017-03-09 13:58:40 -08:00
Wesley W. Terpstra
4535de2669
rocket: use diplomatic interrupts
...
This makes it possible for the PLIC to work with heterogenous cores.
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
d3c5318714
build: remove the now obsolete config string
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
93ca555c20
IntXing: support configurable sync depth
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
7ff9f88ad7
rocket: connect interrupt map for Plic+Clint
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
38489ad9b0
tilelink2: bring IntNode parameters up to the current standard
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
cfd367248f
rocketchip: add blind ports to DTS
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
9a5e2e038b
uncore: add DTS meta-data for devices
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
7f6a250dbf
tilelink2: add hooks for Resources
2017-03-02 21:19:19 -08:00
Henry Cook
6958f05a85
Merge remote-tracking branch 'origin/master' into periphery-adjustments
2017-02-27 19:40:55 -08:00
Andrew Waterman
dfa61bc487
Standardize Data.holdUnless and SeqMem.readAndHold
...
- Make API more idiomatic (x holdUnless y, instead of holdUnless(x, y))
- Add new SeqMem API, readAndHold, which corresponds to most common
use of holdUnless
2017-02-25 03:07:49 -08:00
Wesley W. Terpstra
c01aec9259
tilelink2: support unused IntXing
2017-02-22 18:41:06 -08:00
Wesley W. Terpstra
735e4f8ed6
diplomacy: use HeterogeneousBag instead of Vec
...
This makes it possible for the bundles to have different widths.
Previously, we had to widen all the bundles passing through a node
to the widest of all the possibilities. This would mean that if
you had two source[] fields, they end up the same.
2017-02-22 17:05:22 -08:00
Wesley W. Terpstra
5045696f92
TLRational: test all corners
...
In order to ensure that verilator is happy, we launch both clocks from a
clock divider. Sadly, it does not follow the spec wrt. derived clocks.
See the verilator manual section on "Generated Clocks".
2017-02-17 14:44:31 +01:00
Wesley W. Terpstra
924afebbd9
tilelink2: make TLRational have configurable direction
2017-02-17 13:59:54 +01:00
Wesley W. Terpstra
abe344a1a4
tilelink2 Fuzzer: support read-only mode ( #555 )
2017-02-13 00:18:47 +01:00
Henry Cook
e8c8d2af71
Heterogeneous Tiles ( #550 )
...
Fundamental new features:
* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.
Additional changes that got rolled in along the way:
* rocket: Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
2017-02-09 13:59:09 -08:00
Wesley W. Terpstra
7afe383db3
Ecc: detect uncorrectable errors also for SEC
2017-02-03 16:21:09 -08:00
Wesley W. Terpstra
7aba066e67
tilelink2: add TLZero; /dev/zero suitable for putting behind locked cache ways
2017-02-03 16:20:27 -08:00
Jacob Chang
83a83c778a
Added range function in IdRange
...
Added source accessor function in TLEdge
2017-02-02 12:35:57 -08:00
Wesley W. Terpstra
e5af59db68
rocketchip: work-around ucb-bar/chisel3#472
2017-01-31 14:20:02 -08:00
Wesley W. Terpstra
f7f52cc722
diplomacy: restore Monitor functionality
2017-01-29 17:25:14 -08:00
Wesley W. Terpstra
972953868c
uncore: switch to new diplomacy Node API
...
Most adapters should work on multiple ports.
This patch changes them all.
2017-01-29 15:54:45 -08:00
Wesley W. Terpstra
830d01329d
RationalCrossing: add some documentation
2017-01-26 21:27:34 -08:00
Wesley W. Terpstra
fc3b72084f
tilelink2: add a rational clock crossing adapter
2017-01-26 20:07:28 -08:00
Wesley W. Terpstra
4b70386393
AsyncCrossing: disambiguate the file name
2017-01-26 20:07:28 -08:00
Wesley W. Terpstra
6ff35a387a
tilelink2: disable A=>D bypass in ToAXI4 whenever possible
2017-01-24 18:11:00 -08:00
Wesley W. Terpstra
64e1de751d
axi4: add a minLatency parameter
2017-01-24 18:11:00 -08:00
Wesley W. Terpstra
c0b6d31377
tilelink2: Delayer adapter useful for unit tests
2017-01-23 15:50:39 -08:00
Wesley W. Terpstra
9dc7f180b6
diplomacy: support zero-port Nodes
2017-01-19 19:08:01 -08:00
Wesley W. Terpstra
e7b35b4bb6
diplomacy: support multiple ports behind a BlindNode
2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
4bdb2e5d68
tilelink2 Monitor: ReleaseAck source does not count
2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
fbf1073586
tilelink2: CacheCork - terminate caching
2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
bf7823f1c8
tilelink2: split suportsAcquire into T and B variants
2017-01-19 19:07:13 -08:00
Henry Cook
74b6a8d02b
Refactor Tile to use cake pattern ( #502 )
...
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
2017-01-16 18:24:08 -08:00
Jacob Chang
c531093898
Fix bug introduced with Fuzzer when nOperations is power of 2 ( #492 )
2016-12-15 19:10:53 -08:00
Wesley W. Terpstra
a9b264e582
ahb: lower hsel when idle to save power
2016-12-15 15:32:30 -08:00
Wesley W. Terpstra
16febe7e94
apb: add a TileLink to APB bridge and unittest it
2016-12-15 15:32:27 -08:00
Wesley W. Terpstra
ed091f55e6
apb: diplomatic APB framework
2016-12-15 13:48:50 -08:00
Wesley W. Terpstra
a5b8fc2317
RegisterRouterTest: start up with 0 in registers to make VIP testing easier
2016-12-14 15:38:08 -08:00
Wesley W. Terpstra
9d50704b64
ahb: don't violate spec with SRAM fuzzing
2016-12-14 15:18:41 -08:00
Jacob Chang
aae9b23036
Update with paratermized LazyModule
2016-12-12 16:16:56 -08:00
Jacob Chang
762afcd54a
Merge remote-tracking branch 'origin/master' into jchang_test
2016-12-09 16:56:49 -08:00
Jacob Chang
4c3083c181
Remove unnecessary val
2016-12-09 16:44:30 -08:00
Wesley W. Terpstra
09afbbafdb
ahb: weaken RegisterRouter assertion
...
As written I think it could potentially fail, but what I actually care
about is something weaker that should be true. Assert: nothing lost.
2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
588b944ed4
ahb: implement and test address decoding
2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
5d1064fcb1
ahb: include a unit test
2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
51dfb9cb06
ahb: TileLink master
2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
01b0f6a52b
ahb: new diplomacy-based AHB bus definition
2016-12-08 18:00:39 -08:00
Jacob Chang
54cc071a64
Fix Fragmenter to ensure logical operations must be sent out atomically.
...
Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0
2016-12-07 16:22:05 -08:00
Wesley W. Terpstra
c2eedbfe23
tilelink2 Monitor: use Parameters instead of global variables
2016-12-07 12:24:03 -08:00
Wesley W. Terpstra
020fbe8be9
diplomacy: make config.Parameters available in bundle connect()
...
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
Wesley W. Terpstra
fbfa15efea
TLBroadcast: support non-FIFO devices ( #482 )
2016-12-05 22:10:37 -08:00
Wesley W. Terpstra
3c9718ec8f
clint: undefined registers must be zero ( #480 )
...
This is needed so that SMP-safe boot loaders can safely
read/write to the IPI register of non-existent harts.
2016-12-05 17:11:53 -08:00
Jacob Chang
cff2612cdb
minor Changes needed to support formal tests
2016-12-01 15:02:23 -08:00
Wesley W. Terpstra
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
a0e10aec05
uncore: removed obsolete Builder file
2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
30e890b480
diplomacy: include InternalNodes for AXI4 and TL
2016-11-23 20:44:45 -08:00
Henry Cook
38c5af5bad
[rocket] cleanup mshr logic
2016-11-23 12:09:56 -08:00
Henry Cook
dae6772624
factor out common cache subcomponents into uncore.util
2016-11-23 12:09:35 -08:00
Wesley W. Terpstra
1d3cad3671
tilelink2 SourceShrinker: handle degenerate cases for free
2016-11-22 22:17:30 -08:00
Wesley W. Terpstra
c0b27999ea
tilelink2 SourceShrinker: a concurrency reducing adapter
2016-11-22 21:43:38 -08:00
Wesley W. Terpstra
0097274ea3
Broadcast: single-cycle response is possible
2016-11-22 20:45:40 -08:00
Wesley W. Terpstra
c80ee06472
rocketchip: configString is a lazy property of outer
2016-11-22 17:27:58 -08:00
Henry Cook
28c6be90ab
[rocket] require refillcycesperbeat == 1 and remove flowthroughserializer
2016-11-20 19:36:51 -08:00
Henry Cook
c31b41a7ac
[tl2] add grant finisher comment
2016-11-19 19:16:43 -08:00
Wesley W. Terpstra
d1328a6b6f
rocketchip: remove most uses of GlobalAddrMap
2016-11-18 19:38:02 -08:00
Henry Cook
8b908465e0
[tl2] convert NBDcache to TL2 (WIP; compiles but untested)
2016-11-18 19:04:06 -08:00
Henry Cook
5f1cc19d71
[tl2] fix comment explaining permissions
2016-11-18 19:02:17 -08:00
Henry Cook
10112da4e7
[tl2] won't need putthrough opcode
2016-11-18 19:02:17 -08:00
Wesley W. Terpstra
5b594ced29
Plic: support 0 interrupts gracefully
2016-11-18 18:07:44 -08:00
Wesley W. Terpstra
03bca77b33
tilelink2 Metadata: cannot assert data good when !valid
2016-11-18 17:16:12 -08:00
Wesley W. Terpstra
37a3c22639
rocketchip: move from using cde to config
2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
e5febcfa33
rocketchip: there are no more useful parameters to dump
2016-11-18 14:31:42 -08:00
Wesley W. Terpstra
30425d1665
rocketchip: eliminate all Knobs
2016-11-18 14:31:42 -08:00
Wesley W. Terpstra
119ccae9af
rocketchip: don't use explicit cde namespace
2016-11-18 14:31:42 -08:00
Henry Cook
94086f2270
[tl2] broadcast hub probe port width bugfix
2016-11-17 18:42:59 -08:00
Henry Cook
960c2723ab
[tl2] MemoryOpCategories: use def to supply Cat'd consts
2016-11-17 18:42:59 -08:00
Wesley W. Terpstra
dfc3a0dafb
tilelink2: do not depend on obsolete TL1 configuration
2016-11-17 14:07:53 -08:00
Henry Cook
24e3216fcf
coreplex: allow zero interrupt sink/sources
2016-11-16 16:50:36 -08:00
Henry Cook
479bc82f03
tilelink2 Broadcast: improve bufferless throughput
2016-11-16 16:50:36 -08:00
Henry Cook
1f51564577
[rocket] dcache probe ack data bugfix
2016-11-16 14:25:21 -08:00
Wesley W. Terpstra
5d2e637a4a
tilelink2 Legacy: uncached TL never needs manager_xact_id
2016-11-16 12:16:25 -08:00
Wesley W. Terpstra
10e459fedb
rocket: change connection between rocketchip and coreplex
...
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
2016-11-15 18:27:52 -08:00
Wesley W. Terpstra
ab3dafb8bc
Monitor: restore Probe&Acquire checks
2016-11-14 15:36:52 -08:00
Wesley W. Terpstra
385b5d5698
axi4: default should be GET_EFFECTS
2016-11-14 15:19:39 -08:00
Henry Cook
c0efd247b0
[tl2] expand firstlast api and L1WB bugfix
2016-11-14 12:12:31 -08:00
Henry Cook
b7730d66f2
WIP bugfixes: run until corrupted WB data (beats repeated)
2016-11-11 18:34:48 -08:00
Henry Cook
71315d5cf5
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
Henry Cook
afa1a6d549
WIP uncore and rocket changes compile
2016-11-10 15:57:29 -08:00
Wesley W. Terpstra
9d77e34bee
tilelink2 Filter: make transfer cap robust against large filters
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
b8df59f43b
tilelink2 Broadcast: support "bufferless" implementation
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
14800f8fb4
tilelink2 Broadcast: only support caching readable devices
2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
0f3947bb86
tilelink2 Broadcast: add special case handling for 0 cached clients
2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
ba3c83287f
tilelink2 Xbar: merge the AddressSets of fractured managers
2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
55326c29bb
tilelink2: Filter adapter removes some of the address space
2016-11-03 22:18:23 -07:00
Wesley W. Terpstra
86ba94781b
tilelink2: broadcast coherence manager
2016-11-03 14:37:19 -07:00
Wesley W. Terpstra
d067e87a7d
tilelink2 Parameters: sinkId is per port, not per manager
2016-11-03 14:37:17 -07:00
Wesley W. Terpstra
ed4224dde4
tilelink2 AtomicAutomata: fix AccessAck on same cycle as PutFull
...
If we send out the PutFull portion of an AMO, the slave is allowed
to respond with AccessAck on the same cycle. In this case, we are
still in the AMO state, but must still match the D response.
2016-10-31 15:17:10 -07:00
Wesley W. Terpstra
a12fea51e8
Plic: skip reserved interrupt in interrupt map printout
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
ba529c3716
rocketchip: use TileLink2 interrupts
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
043ed48c8c
tilelink2 HintHandler: delay answers to help TL1 legacy clients
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
015c3b862a
diplomacy: print out bus widths on edges in agent graph
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
0cc00e7616
regressions: test scratchpad
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
d2e9fa8ec6
Plic: remove path from ready to bits
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
545154c1c3
groundtest: make it happy with TL2 addressing
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
9a26cb7ec7
Debug: mark the debug device executable
2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
89139a9492
Plic: split constants from variables used in config string
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
11121b6f4c
rocket: convert scratchpad to TL2
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
f8a0829134
rocketchip: remove clint; it moves into coreplex
2016-10-31 11:42:13 -07:00
Megan Wachs
5090ff945b
DebugModule: Be more paranoid about addressing corner cases.
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
b99662796d
PLIC: converted to TL2
2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
bddfa4d69b
Debug: make address configurable
2016-10-31 11:42:13 -07:00
Megan Wachs
10d084b9f3
DebugModule: Use the power of RegisterRouter to simplify the DebugROM code.
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
650f6fb23f
diplomacy: add BlindNodes for use as external ports
2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
0edcd3304a
diplomacy Nodes: leave flipping to the MixedNode implementation
2016-10-31 11:41:18 -07:00
Megan Wachs
d530ef7236
DebugModule: translate to TL2 with {32,64}-bit XLen width
2016-10-31 11:41:18 -07:00
Howard Mao
f0e9a2a081
Fix PutBlock after Release bug
...
There is logic in the broadcast hub to skip the outer acquire if there
is an outgoing release, since the data will be written out through the
release channel. However, this will cause an issue in the case of
PutBlock requests. If the tail beats of the PutBlock show up after the
outer release has already been sent, the data will be corrupted.
The fix is to make the outer release block if there are pending
inner PutBlock beats.
2016-10-28 18:26:34 -07:00
Andrew Waterman
e45b41b4b6
Don't rely on SeqMem output after read-enable is low
2016-10-27 23:44:10 -07:00
Howard Mao
900a7bbcf1
add PutAtomic support to width adapter
2016-10-26 09:58:26 -07:00
Wesley W. Terpstra
fee67c4abf
diplomacy: add methods to find {out,in}ner-most common node
2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
67ab27f5a5
diplomacy: guess the LazyModule name from the containing class
2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
4d50733548
tilelink2 ToAXI4: use helper method for a_last ( #418 )
2016-10-25 10:16:42 -07:00
Wesley W. Terpstra
a5ac106bb8
axi4 ToTL: fix decode error arbitration ( #417 )
...
When selecting between error generation on R and real data on R,
correctly calculate the R backpressure.
This bug manifests when a valid request is immediately followed by
an invalid request, wedging the R channel.
2016-10-24 22:15:19 -07:00
Wesley W. Terpstra
4c815f7958
tilelink2 Parameters: fix {contains,supports}Safe ( #416 )
...
When there is only one manager, you still want to know if the address
was wrong on the link to that manager!
2016-10-24 20:37:04 -07:00
Wesley W. Terpstra
8bfd6bcd4d
axi4: ensure we accept AR before reporting R ( #411 )
2016-10-21 21:02:05 -07:00
Wesley W. Terpstra
7c334e3c34
axi4 ToTL: shorter critical path on Q.bits if errors go first
2016-10-17 01:00:49 -07:00
Wesley W. Terpstra
73010c79a3
axi4 ToTL: handle bad AXI addresses
2016-10-17 00:12:26 -07:00
Wesley W. Terpstra
501d6d689f
axi4: Test ToTL
2016-10-16 22:04:06 -07:00
Wesley W. Terpstra
5a1da63b5a
axi4: prototype ToTL adapter
2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
72e5a97d40
tilelink2: factor out the OH1ToOH function
2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
d09f43c32f
axi4 Bundles: add a size calculation helper
...
The old version was wrong.
Inverting before the << has a different width.
This means you end up with high bits set.
2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
20288729b9
tilelink2 Isolation: cross the valid signals as well
...
Refactor the code to be less copy-pasty
2016-10-14 18:28:36 -07:00
Wesley W. Terpstra
ac0bb841da
AsyncQueue: cope with far reset propagation delay
2016-10-14 18:05:35 -07:00
Wesley W. Terpstra
8f3c2ddfc3
tilelink2 Crossing: these asserts should be done by the AsyncQueue
2016-10-14 16:54:09 -07:00
Wesley W. Terpstra
a82cfb8306
tilelink2: replace addr_hi with address ( #397 )
...
When faced with ambiguous routing of wmask=0, we decided to include
all the address bits. Hopefully in most cases the low bits will be
optimized away anyway.
2016-10-14 14:09:39 -07:00
Wesley W. Terpstra
54b73aef57
tilelink2: WidthWidget and Fragmenter no longer erase latency
2016-10-13 17:02:18 -07:00
Wesley W. Terpstra
200cf3dd13
tilelink2 Nodes: include some options to test for conformance
2016-10-13 17:02:18 -07:00
Wesley W. Terpstra
5d5b5a66f4
tilelink2 RAMModel: fix a write-bad-data bug
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
e5a1483358
tilelink2 Fragmenter: eliminate most of the registers on A
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
99c7003d11
tilelink2: allow preemption of Fragmenter and WidthWidget
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
b42cfdc9dd
tilelink2 Arbiter: there is only one winner
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
b6e9b0c558
tilelink2 Arbiter: allow preemption of first beat
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
0aebf9e341
tilelink2 ToAXI4: no arbitration path register needed
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
0e897b905f
tilelink2 RegisterRouter: data path register is no longer required
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
c4eadd3ab3
tilelink2 Monitor: enforce stricter transaction ordering
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
d8a1163131
tilelink2 Monitor: don't enforce Irrevocable any more
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
405f66da32
tilelink2 WidthWidget: cope with Decoupled inputs
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
e2e72ac979
tilelink2 Fragmenter: cope with Decoupled input
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
023c6402e9
tilelink2: switch to DecoupledIO syntax
2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
4c1c52486b
axi4 Fragmenter: handle more inflight AXI requests than we have space
2016-10-13 15:52:32 -07:00
Wesley W. Terpstra
8005266131
axi4 Fragmenter: refine sideband FSM for case of last fragment
2016-10-13 15:52:32 -07:00
Wesley W. Terpstra
19064e602b
axi4 Fragmenter: align all output accesses
...
We promised the output is aligned. Make good on that!
2016-10-13 15:52:27 -07:00
Wesley W. Terpstra
84be93f9f3
axi4 Fragmenter: confirm correct handling of last
2016-10-13 14:01:23 -07:00
Wesley W. Terpstra
1c79a23a8b
axi4 Fragmenter: initialize error response to 0
2016-10-13 13:46:24 -07:00
Wesley W. Terpstra
958af132ba
axi4 Fragmenter: optimize dynamic slave lookup
2016-10-12 17:29:38 -07:00
Wesley W. Terpstra
11169d155c
axi4: add a Buffer to put between nodes
2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
a9a3f7dd4e
tilelink2 RAMModel: include name of test in output
2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
345eefd81b
axi4: include unit tests
2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
a6c6d99848
axi4: prototype Fragmenter
2016-10-12 17:08:49 -07:00
Wesley W. Terpstra
c918aa6d89
axi4: name AdapterNode parameters properly
2016-10-12 17:02:02 -07:00
Wesley W. Terpstra
a423f97844
axi4: parameterized AXI master constraint for aligned access
2016-10-12 17:02:02 -07:00
Wesley W. Terpstra
673cf1fdb5
tilelink2 ToAXI4: must create irrevocable D for now
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
8e92ac32b7
tilelink2 ToAXI4: we need a Queue on B to guarantee deadlock freedom
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
38b6c1c820
tilelink2 axi4: RegisterRouter can cut ready dependency
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
dc26736f32
axi4 tilelink2: include minAlignment and maxAddress in slaves
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
538437384a
tilelink2 Fragmenter: combine AccessAck errors
2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
4caa543ad7
tilelink2: Fragmenter should not cut Acquire parameters
...
The correct response to misuse is to fail a requirement check.
Pretending that things are not caches could lead to inconsistency.
2016-10-11 22:38:03 -07:00
Wesley W. Terpstra
6336f94fa2
tilelink2: only caches can support B requests
2016-10-11 22:38:02 -07:00
Wesley W. Terpstra
4a975ca380
tilelink2: add a rightOR to go with our leftOR
2016-10-11 22:38:02 -07:00
Wesley W. Terpstra
b0e33f4a39
tilelink2: use TLArbiter in HintHandler
2016-10-10 13:15:28 -07:00