This clarifies and provides consistent for the command line arguments
usage text.
This adds a set of examples for running the rocket-chip emulator.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
This, with riscv-fesvr modifications, enables the rocket-chip emulator
to understand (and error out) if a command line argument that will
eventually be consumed by HTIF looks bad and can error out quickly.
This relies on modifications to risc-fesvr to support getopt and the
exposure of what HTIF arguments exist via the `htif.h` header.
Revision 7e79421 (issue #484) makes emulator.cc rejecting any unrecognized
+arg "legacy" arguments, however, this breaks riscv-torture emulator tests
as it needs to pass +signature to the DTM.
I think it is actually impossible to check for unknown argument here
unless we hardcode a list of all arguments recognized by fesrv. Fix this
issue by passing all arguments starting with the first unknown argument
to DTM.
Updates #484.
Signed-off-by: Minux Ma <minux.ma@gmail.com>
This changes the emulator to conform to POSIX-style options (e.g.,
short/'-' and long/'--') while preserving legacy option parsing (i.e.,
'+'). Options are read from the user until the first
non-option (either POSIX or legacy) is encountered. This and
everything following is assumed to be the binary and any arguments the
user wants to run on the emulator. All non-options are passed directly
to the DTM. This allows for the same option to be passed, safely, to
both the emulator and the binary, e.g., "+verbose".
This introduces a dependency on <getopt.h>.
Closes#484.
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected). However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary. Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.
This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence. The main blocker is the lack of Verilog parameterization for
BlackBox. It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL. But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
Megan Wachs
Schuyler Eldridge
Wesley W. Terpstra
Andrew Waterman
Minux Ma
Andrew Waterman
Henry Cook
Howard Mao
Scott Beamer
Colin Schmidt
Andrew Waterman
Donggyu Kim
Yunsup Lee
Iori YONEJI
Henry Cook