e6661a6982
Debug regressions: use a plusarg to enable remote bitbang.
2018-01-05 17:08:21 -08:00
b643f3dca6
debug regressions: some whitespace and null ptr cleanup
2018-01-05 17:08:21 -08:00
96dd5d8c38
Emulator example clarifications
...
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-05 17:08:21 -08:00
7ae6bf7611
Arguments clarification, add examples
...
This clarifies and provides consistent for the command line arguments
usage text.
This adds a set of examples for running the rocket-chip emulator.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-05 17:08:21 -08:00
1aa87f6578
Make emulator.cc understand HTIF arguments
...
This, with riscv-fesvr modifications, enables the rocket-chip emulator
to understand (and error out) if a command line argument that will
eventually be consumed by HTIF looks bad and can error out quickly.
This relies on modifications to risc-fesvr to support getopt and the
exposure of what HTIF arguments exist via the `htif.h` header.
2018-01-05 17:08:21 -08:00
3ead9a5d2d
Move check on VCS inside riscv-fesvr
...
This removes the necessary preprocessing of riscv-fesvr arguments to
avoid situations where riscv-fesvr thinks that an argument is the
binary. Support for this is rolled into riscv-fesvr.
2018-01-05 17:08:21 -08:00
a97add954a
Async Reg: Doesn't properly reset for Verilator.
2018-01-05 17:08:21 -08:00
9df3604007
emulator: No reason not to emit waveforms during reset
2018-01-05 17:08:21 -08:00
024cd52c44
debug: attempt to make the simulation deterministic by not returning until connection is made and command is receieved
2018-01-05 17:08:21 -08:00
1d3fa07c44
debug: print failures when debug tests fail, so we can see why it is failing on Travis
...
Cleanups, and print out log names ASAP.
Factor out gdbserver common invocation into GDBSERVER (fixing
--print-failtures).
Add --print-log-names to that command so the logfiles can be inspected
while the simulation is still running.
`RISCV=... cmd` is more idiomatic than `export RISCV=... && cmd`
2018-01-05 17:08:15 -08:00
9b234216f0
debug: Install pexpect package for travis regressions
2018-01-05 16:13:19 -08:00
1549ecfb3f
debug: explicitly clone riscv-tests to get to gdbserver.py
2018-01-05 16:13:11 -08:00
3de9a04272
debug regression: until XLEN fix is merged into riscv-tests, have to explicitly state the XLEN
2018-01-05 16:10:13 -08:00
bd5fe5d22e
Debug regression: have to say something about memory in order to run a simple test
2018-01-05 16:10:13 -08:00
5df55d7911
debug regression: bump riscv-tools for riscv-tests fixes
2018-01-05 16:10:13 -08:00
593839e0d5
Debug: add Debug regression to Travis regressions.
2018-01-05 16:10:00 -08:00
4449dd0baa
Debug regressions: Add necessary config scripts
2018-01-05 16:03:59 -08:00
e82328336e
Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.
...
This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
2018-01-05 16:02:52 -08:00
206892899f
Merge pull request #1171 from freechipsproject/fix-msb-check
...
Enforce physical-address canonicalization
2018-01-03 12:06:18 -08:00
1bd343bcef
Merge pull request #1156 from freechipsproject/has-tiles
...
coreplex: make HasTiles more generic
2018-01-02 19:38:17 -08:00
ee1a9485df
Enforce physical-address canonicalization
...
When xLen > paddrBits, enforce that physical addresses are zero-extended.
This works by checking that the _virtual_ address is _sign_-extended, then
checking that its sign is positive.
2018-01-02 18:47:30 -08:00
7c9a1b0265
Correctly check for virtual-address canonicalization
...
The previous check was necessary but not sufficient.
2018-01-02 18:41:25 -08:00
320900f76c
tile: BaseTileModule => BaseTileModuleImp
2018-01-02 17:55:54 -08:00
b0e1bc3071
tile: cake reduction
...
* merge HasScratchpadSlavePort into RocketTile
* merge CanHaveSharedFPUModule into BaseTileModule
2018-01-02 17:49:08 -08:00
efe7165b54
tile: BaseTile refactor, pt 2
...
* 2 layer cake
* no more bundle traits, only call to IO
2018-01-02 15:37:31 -08:00
1579ddb97e
tile: removed RocketTileWrapper. RocketTile now HasCrossing.
2017-12-28 14:00:13 -08:00
1cd018546c
tile: BaseTile refactor, pt 1
...
* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
2017-12-26 11:04:15 -08:00
ba6dd160a3
diplomacy: allow access to sram Device info
2017-12-22 19:00:43 -08:00
7385c99435
Bump chisel3 and firrtl to get bug fixes ( #1163 )
...
Fixes #1160
2017-12-20 19:06:38 -08:00
d9c5ec4f7b
coreplex: HasTiles supplies def tileParams
2017-12-20 17:18:55 -08:00
ddaeedf2d0
coreplex: make HasTiles more generic
...
HasTiles now deals with only extremely general tile IOs.
Some RocketTiles specific behavior moved into RocketCoreplex.
BaseTile now has optional LocalInterruptNode.
2017-12-20 17:18:55 -08:00
9b82f1098d
Merge pull request #1154 from freechipsproject/bump-sbt
...
Bump chisel, firrtl, and sbt
2017-12-19 14:16:47 -08:00
895c4b9261
Revert "ICache: stores to the ITIM have effects (shrinking valid ITIM data) ( #1144 )" ( #1162 )
...
This reverts commit a542ae687e
2017-12-19 12:16:26 -08:00
74d9326ebc
JTAG: Revert to Chisel._ for Issue 1160 ( #1161 )
...
* JTAG: Revert to Chisel._ for Issue 1160
* JTAG: Revert to Chisel._ for Issue 1160
* jtag: revert everything to Chisel._
* jtag: Revert all modules to Chisel._ vs chisel3, due to FIRRTL issues with chisel3 generated code
2017-12-18 21:02:31 -08:00
a31ba2ea2e
diplomacy: LazyModule factory uses ValName ( #1159 )
...
* diplomacy: LazyModule factory uses ValName
2017-12-18 15:40:30 -08:00
3df401eef7
Bump chisel3 and firrtl and bump sbt to version 1.0.4
...
sbt bump must be accompanied by bump to chisel3 and firrtl using sbt
1.0.4
2017-12-18 12:09:21 -08:00
b914564a62
Move build.scala -> build.sbt
2017-12-18 12:08:51 -08:00
0b2d200e91
Bump scala and sbt-site plugin versions.
2017-12-18 12:08:33 -08:00
09160d0cd5
Changed label for DCache and ICache error covers + take away exclusio… ( #1155 )
...
* Changed label for DCache and ICache error covers + take away exclusion that shouldn't be there
* rocket: add d-channel error to I$
2017-12-13 20:16:36 -08:00
a542ae687e
ICache: stores to the ITIM have effects (shrinking valid ITIM data) ( #1144 )
2017-12-08 17:35:14 -08:00
c2a0319dc4
Merge pull request #1151 from freechipsproject/error-atoms
...
Error atomics
2017-12-08 17:34:55 -08:00
efc793d52e
CloneModule: must be public to be used in pattern matches
2017-12-08 14:57:08 -08:00
2ca03384ec
diplomacy: skip anonymous class names
2017-12-08 14:36:12 -08:00
588dacec17
Bump Chisel and Firrtl ( #1134 )
2017-12-08 14:22:18 -08:00
18b8a61775
Error device: require explicit control of atomic and transfer sizes
2017-12-08 13:41:09 -08:00
6a0150aad7
Error device: mark executable to support testing erroneous I$ refill
2017-12-08 12:38:06 -08:00
9cc37b8444
Merge pull request #1150 from freechipsproject/fix-uncached-unaligned-fetch
...
Prevent frontend deadlock fetching from uncacheable memory
2017-12-08 11:02:44 -08:00
676110bc1f
Add cover for a1ebe6da4d
2017-12-07 21:03:42 -08:00
a1ebe6da4d
Prevent frontend deadlock fetching from uncacheable memory
...
After detecting a corrupted BTB, don't speculatively update it until
the next non-speculative fetch. This prevents the frontend from replaying
forever.
2017-12-07 18:56:06 -08:00
ec3789b365
Add Cross Cover Property Library ( #1149 )
...
Add cover points related to memory error to I/D Cache
2017-12-07 18:46:10 -08:00
Megan Wachs
Schuyler Eldridge
Andrew Waterman
Henry Cook
Andrew Waterman
Jack Koenig
Jack Koenig
Jim Lawson
Jacob Chang
Wesley W. Terpstra
Gleb Gagarin