Andrew Waterman
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42970c9a99
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Update Rocket
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2013-09-15 04:39:52 -07:00 |
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Andrew Waterman
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628745226c
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Use spike disassembler riscv-dis if it exists
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2013-09-15 04:25:53 -07:00 |
|
Andrew Waterman
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80003b3019
|
Support RoCC
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2013-09-15 04:25:26 -07:00 |
|
Andrew Waterman
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fbdbb01232
|
update to new isa; disable vector tests
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2013-09-12 17:04:03 -07:00 |
|
Henry Cook
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b42e140e05
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NetworkIOs no longer use thunks
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2013-09-10 16:23:52 -07:00 |
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Stephen Twigg
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6cde69e95d
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Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc.
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2013-09-09 14:31:18 -07:00 |
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Stephen Twigg
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f27c0fb010
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Merge commit '2bd4a66eee572252ba6250f9bddada51657fc379' into chisel-v2
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2013-09-05 15:01:56 -07:00 |
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Stephen Twigg
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69daae0dae
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Add dependency resolvers to build.scala to fix build script
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2013-09-05 14:56:41 -07:00 |
|
Yunsup Lee
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2c47b4388a
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push rocket
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2013-08-26 14:54:49 -07:00 |
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Yunsup Lee
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9003bc2614
|
push rocket
|
2013-08-24 22:42:57 -07:00 |
|
Yunsup Lee
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d0674af13f
|
forgot to push riscv-rocket
|
2013-08-24 22:15:38 -07:00 |
|
Yunsup Lee
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ba9bbc27df
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apply same change to fpga top-level
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2013-08-24 15:50:03 -07:00 |
|
Yunsup Lee
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76cd90fc01
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parameterize number of SCRs
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2013-08-24 15:47:42 -07:00 |
|
Yunsup Lee
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694ebd65cf
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push uncore
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2013-08-24 15:24:25 -07:00 |
|
Yunsup Lee
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0884bc9789
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fix DRAMSideLLCNull entries
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2013-08-24 13:20:38 -07:00 |
|
Yunsup Lee
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1e3ac0afa9
|
back to NTILES=1
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2013-08-24 13:10:30 -07:00 |
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Henry Cook
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6aa500fc16
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dont make assumptions about default project name when invoking sbt
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2013-08-20 12:56:01 -07:00 |
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Henry Cook
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b06d33da2f
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Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
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2013-08-19 19:54:41 -07:00 |
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Henry Cook
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85e5ce046f
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pulled submodule commits, uncore sbt standardized
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2013-08-15 17:07:13 -07:00 |
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Henry Cook
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6b20556661
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Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2
Conflicts:
chisel
riscv-hwacha
riscv-rocket
uncore
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2013-08-15 16:39:30 -07:00 |
|
Henry Cook
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784e017bae
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Final Reg standardization
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2013-08-15 16:37:58 -07:00 |
|
Henry Cook
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9b70ecf546
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Reg standardization
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2013-08-13 17:53:19 -07:00 |
|
Huy Vo
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d7d13255db
|
chisel tag
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2013-08-12 20:53:29 -07:00 |
|
Huy Vo
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f9d1403a92
|
tags
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2013-08-12 20:53:17 -07:00 |
|
Huy Vo
|
cc6631ae4d
|
reset -> _reset
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2013-08-12 20:52:55 -07:00 |
|
Henry Cook
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11e131af47
|
initial attempt at upgrade
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2013-08-12 10:46:22 -07:00 |
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Henry Cook
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199e76fc77
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:31:27 -07:00 |
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Stephen Twigg
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c1b1a21a0f
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If +stats is set when running simv-debug, will only output vcd data when cr28 is high.
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2013-07-30 16:39:47 -07:00 |
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Henry Cook
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4d916b56e3
|
Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file.
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2013-07-24 23:28:43 -07:00 |
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Stephen Twigg
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3f874342a4
|
Update chisel to appropriate version for reference chip build.
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2013-07-10 17:08:56 -07:00 |
|
Ben Keller
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c7bf1aaac9
|
Merge branch 'master' of github.com:ucb-bar/reference-chip
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2013-07-10 16:01:25 -07:00 |
|
Ben Keller
|
a72e0dc99e
|
Updated riscv-tools reference
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2013-07-10 16:01:01 -07:00 |
|
Henry Cook
|
2796de01bf
|
new tilelink arbiter types, reduced release xact trackers
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2013-07-09 15:41:27 -07:00 |
|
Andrew Waterman
|
c5f01f3f87
|
update rocket
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2013-06-15 00:55:34 -07:00 |
|
Andrew Waterman
|
4ae0c68303
|
require -std=c++11, as -std=c++0x doesn't cut it
|
2013-06-14 00:28:42 -07:00 |
|
Henry Cook
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896179cbb6
|
removed bad mt test
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2013-06-14 00:14:18 -07:00 |
|
Henry Cook
|
85fbb650c9
|
makefile support for new multithreading tests
|
2013-06-13 15:34:54 -07:00 |
|
Andrew Waterman
|
ae0716fb6d
|
Use chisel printf for logging
|
2013-06-13 10:53:23 -07:00 |
|
Stephen Twigg
|
bd43ca8423
|
Merge branch 'master' of github.com:ucb-bar/reference-chip
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2013-05-23 17:51:24 -07:00 |
|
Henry Cook
|
c06cbf523b
|
Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore.
|
2013-05-23 15:26:20 -07:00 |
|
Henry Cook
|
6a69d7d7b5
|
pass closure to generate bank addr
|
2013-05-23 14:58:19 -07:00 |
|
Yunsup Lee
|
26ed805862
|
push chisel,riscv-rocket,uncore
linux kernel boots!
|
2013-05-21 19:00:40 -07:00 |
|
Yunsup Lee
|
f3c78abc2b
|
push riscv-tests
|
2013-05-16 00:51:02 -07:00 |
|
Yunsup Lee
|
e77bde71d0
|
push riscv-tools
|
2013-05-15 12:03:52 -07:00 |
|
Yunsup Lee
|
f0b0867f5a
|
push riscv-tests
|
2013-05-13 19:22:28 -07:00 |
|
Yunsup Lee
|
f13605d2f5
|
push riscv-tools
|
2013-05-13 19:14:57 -07:00 |
|
Yunsup Lee
|
7ba3ab03e2
|
update README
|
2013-05-13 11:19:55 -07:00 |
|
Yunsup Lee
|
5b55cc93af
|
add submodule riscv-tools
|
2013-05-10 11:53:55 -07:00 |
|
Andrew Waterman
|
e8fcdb56a6
|
update chisel to work around xilinx ise bug
|
2013-05-03 01:47:15 -07:00 |
|
Andrew Waterman
|
d825c9d6e9
|
make fpga Makefile work with updated Makefrag
|
2013-05-02 05:09:45 -07:00 |
|