riscv/rocket-chip
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Author SHA1 Message Date
Megan Wachs
c78ee9f0e4 syncreg: Refactor common code 2017-08-24 17:18:04 -07:00
Megan Wachs
d83a6dc6af syncregs: Add utilities for Synchronizing Shift Registers 2017-08-24 16:55:17 -07:00
Megan Wachs
bdaae40035 Merge pull request #973 from freechipsproject/named_buffers 
systemBus: allowing naming the TLBuffers which get inserted
 2017-08-24 16:31:14 -07:00
Megan Wachs
7f683eeb24 async_regs: Make modules have predictable names 2017-08-24 15:33:53 -07:00
Megan Wachs
0f75ebee92 async_reg: Rename the file to match scalastyle 2017-08-24 15:31:29 -07:00
Megan Wachs
103b6bc6d3 systemBus: allowing naming the TLBuffers which get inserted 2017-08-24 14:49:12 -07:00
Wesley W. Terpstra
17134125e1 SystemBus: remove misnamed functions (#972) 
These functions were actually for cross connecting chips.
 2017-08-24 23:35:01 +02:00
Megan Wachs
6e689f55ed Merge pull request #965 from freechipsproject/quash_x 
async_reset_reg: Squash X's the same as for synchronous reg
 2017-08-21 16:48:25 -07:00
Megan Wachs
81890e3a42 async_reg: Clean up some funky indentation 2017-08-21 16:06:36 -07:00
Megan Wachs
4f45379863 async_reset_reg: Squash X's the same as for reset reg 2017-08-21 14:33:19 -07:00
Andrew Waterman
82df766f4a Merge pull request #963 from freechipsproject/interrupt-order 
Respect ISA requirements on interrupt priority order
 2017-08-18 00:10:19 -07:00
Andrew Waterman
8087a205cc Remove redundant check in interrupt priority encoding 
chooseInterrupts already sorts M interrupts above S interrupts.
 2017-08-17 22:23:42 -07:00
Andrew Waterman
cbe7c51b50 Respect ISA requirements on interrupt priority order 
a62e76cb16
 2017-08-17 21:27:08 -07:00
Shreesha Srinath
b1719cfee0 Fixing requirements for PAddrBits (#961) 
Previously, the requirement for PAddrBits only checked to be equal or greater than the bundle bits. Changing it to check for these to match exactly as for cases when the PAddrBits greater than address bits we could run into scenarios which cause possible address wrap around issues.
 2017-08-17 11:53:59 -07:00
Megan Wachs
1db4b3be9a Merge pull request #957 from freechipsproject/param_jtag_vpi 
jtag_vpi: Use Parameterized Black Box
 2017-08-14 18:37:30 -07:00
Megan Wachs
8783d51c97 jtag_vpi: Use Parameterized Black Box to allow TestHarnesses to override the clock speed 2017-08-14 17:25:47 -07:00
Wesley W. Terpstra
710a782145 HeterogenousBag: empty bags were being combined! (#956) 
This lead to strange firrtl errors when you had two empty
HeterogeneousBags in the same Bundle.
 2017-08-14 15:48:42 -07:00
Andrew Waterman
e945f6e265 Merge pull request #955 from freechipsproject/fix-acquire-before-release 
Fix acquire before release
 2017-08-13 18:29:58 -07:00
Megan Wachs
57a5965bf4 Merge pull request #954 from freechipsproject/max-core-cycles 
Add a +max-core-cycles PlusArg
 2017-08-13 16:45:59 -07:00
Megan Wachs
88332bd885 max-core-cycles: Add a +max-core-cycles PlusArg 2017-08-13 15:47:14 -07:00
Andrew Waterman
3cbc5262ec Don't permit new acquires until the release queue is drained 
If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.
 2017-08-13 13:18:45 -07:00
Andrew Waterman
0190724492 Actually use the C-channel acquire-before-release queue 
oops...
 2017-08-13 13:03:35 -07:00
Andrew Waterman
41a2a03f90 Merge pull request #953 from freechipsproject/fix-dcache-ecc 
Don't trigger ECC writebacks when a release is in flight
 2017-08-12 16:47:19 -07:00
Andrew Waterman
7387f2a93a Don't block D-channel when handling a probe 
This is an acquire-before-release regression.
 2017-08-12 16:13:24 -07:00
Andrew Waterman
604abd5b07 Only report ECC errors when the RAM was actually read 2017-08-12 15:28:03 -07:00
Andrew Waterman
18fb052fc9 DRY 2017-08-12 15:27:30 -07:00
Andrew Waterman
176110b6d3 Don't trigger ECC writebacks when a release is in flight 2017-08-12 15:23:57 -07:00
Wesley W. Terpstra
f191bb994c PatternPusher: can now expect a certain output (#952) 2017-08-11 18:10:27 -07:00
Wesley W. Terpstra
baf769f924 tilelink: add PatternPusher, a device to inject a fixed traffic pattern (#950) 2017-08-11 15:07:10 -07:00
Andrew Waterman
a3358f34a0 Fix priority inversion for two back-to-back divides (#948) 
If the first one is killed for some unrelated reason (e.g. write port
hazard), the second one will still issue to the div-sqrt unit.  While
it will itself later be killed, the fact that the later instruction
acquires a resource needed by the former instruction leads to deadlock.
 2017-08-10 17:12:09 -07:00
Wesley W. Terpstra
fa867bc478 plusarg_reader: make synthesis path a no brainer (#947) 2017-08-10 16:35:30 -07:00
Andrew Waterman
0a591c5b5b Roll back use of UIntToOH1 (#946) 
These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass.  This is not yet conclusive.
 2017-08-09 18:39:47 -07:00
Yunsup Lee
0b8b136831 Merge pull request #943 from freechipsproject/fix-ibuf 
Fix IBuf bug
 2017-08-09 10:38:35 -07:00
Andrew Waterman
721770244e Fix IBuf bug 
Don't examine a packet's xcpt signal if it might be invalid.  In this case,
the correct fix is to not examine xcpt at all; the deleted code was vestigial.
(Note, the other use of xcpt(j+1) in this code is indeed safe.)
 2017-08-09 09:47:51 -07:00
Yunsup Lee
fb2c22ca80 Merge pull request #944 from freechipsproject/fix-vlsi-mem-gen 
memgen: also randomize ren and rand register
 2017-08-08 23:18:08 -07:00
Andrew Waterman
31b75987ca Avoid width warning 2017-08-08 20:57:31 -07:00
Yunsup Lee
8705b0e070 memgen: also randomize ren and rand register 2017-08-08 20:41:53 -07:00
Richard Xia
97ad528a32 Merge pull request #941 from freechipsproject/bump-riscv-tools 
Bump riscv-tools to bump riscv-tests for mi-csr test fix.
 2017-08-08 18:50:29 -07:00
Wesley W. Terpstra
49ba31ac34 Merge pull request #942 from freechipsproject/bus-blocker-lock 
Bus blocker lock
 2017-08-08 18:03:36 -07:00
Wesley W. Terpstra
a9b1410f01 BusBlocker: parameterize page granularity 2017-08-08 17:10:01 -07:00
Wesley W. Terpstra
010ba94474 BusBlocker: rename a variable 2017-08-08 17:00:22 -07:00
Wesley W. Terpstra
6d6fc38787 BusBlocker: lock bit should affect the prior PMP address, not next 2017-08-08 17:00:12 -07:00
Richard Xia
dd5934b6dc Bump riscv-tools to bump riscv-tests for mi-csr test fix and pull in stable binutils. 2017-08-08 16:29:26 -07:00
Yunsup Lee
0a351f677d Merge pull request #940 from freechipsproject/fix-ecc-way 
Don't merge stores that manifest WAW hazards
 2017-08-08 16:05:21 -07:00
Yunsup Lee
8cc41ab46b Merge pull request #936 from freechipsproject/vlsi-mem-gen 
Improve and use vlsi_mem_gen for verilator flow
 2017-08-08 16:04:53 -07:00
Andrew Waterman
809c7e8551 Don't merge stores that manifest WAW hazards 
The following sequence would drop the first store when eccBytes=4:

    sb x0, 0(t0)
    nop
    sb x0, 4(t0)
    nop
    sb x0, 1(t0)

Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.
 2017-08-08 15:19:05 -07:00
Wesley W. Terpstra
3ef6e4c9f2 Merge pull request #939 from freechipsproject/bus-blocker 
tilelink: PMP controlled BusBlocker prevents bus accesses
 2017-08-08 15:06:55 -07:00
Andrew Waterman
82e13443b2 Merge pull request #937 from freechipsproject/critical-paths 
Perform tag error detectoin/correction in same cycle as RAM
 2017-08-08 15:03:28 -07:00
Andrew Waterman
dd103ae7ec Merge pull request #938 from freechipsproject/dtim-ignore-cacheable 
Don't report to the DTIM that data is cacheable
 2017-08-08 15:00:13 -07:00
Wesley W. Terpstra
8f261adc6b BusBlocker: change default policy to deny 2017-08-08 14:19:59 -07:00