152 Commits

Author	SHA1	Message	Date
Wesley W. Terpstra	d755edffcc	DebugTransport: use ToAsyncDebugBus for correct depth	2016-11-25 18:10:28 -08:00
Wesley W. Terpstra	a670f63c81	periphery: a handy trait to turn-off ExtMem	2016-11-23 20:44:45 -08:00
Wesley W. Terpstra	9f1c668c4f	config: when modifying Parameters, subordinate lookups use top	2016-11-23 20:44:45 -08:00
Wesley W. Terpstra	566cc9e60b	rocketchip: RTCPeriod config	2016-11-23 20:44:45 -08:00
Wesley W. Terpstra	e87f54d4f7	rocketchip: traits for adding external TL2 ports	2016-11-23 20:44:42 -08:00
Wesley W. Terpstra	4b9dc78951	rocketchip: add a parameter-controlled debug port	2016-11-23 15:35:53 -08:00
Wesley W. Terpstra	1e7d597fd3	rocketchip: don't waste too many sources on the AXI master port	2016-11-22 21:48:41 -08:00
Wesley W. Terpstra	13190a5de0	rocketchip: re-add AXI4 interface	2016-11-22 17:27:58 -08:00
Wesley W. Terpstra	a140b07009	rocketchip: cut coreplex from rocketchip	2016-11-22 17:27:58 -08:00
Wesley W. Terpstra	c80ee06472	rocketchip: configString is a lazy property of outer	2016-11-22 17:27:58 -08:00
Wesley W. Terpstra	3d644b943c	coreplex: configString is a property of the RISCVPlatform	2016-11-21 21:13:26 -08:00
Wesley W. Terpstra	e8be365b5d	rocketchip: remove GlobalAddrMap completely	2016-11-21 21:13:26 -08:00
Wesley W. Terpstra	d1328a6b6f	rocketchip: remove most uses of GlobalAddrMap	2016-11-18 19:38:02 -08:00
Wesley W. Terpstra	001d9821bd	Merge remote-tracking branch 'origin/master' into tl2-tile	2016-11-18 18:19:41 -08:00
Wesley W. Terpstra	a6188efc41	rocketchip: break infinite Config loops	2016-11-18 16:18:33 -08:00
Wesley W. Terpstra	37a3c22639	rocketchip: move from using cde to config	2016-11-18 16:18:33 -08:00
Wesley W. Terpstra	30425d1665	rocketchip: eliminate all Knobs	2016-11-18 14:31:42 -08:00
Richard Xia	bab504cc3f	Add various granular and composable configs.	2016-11-18 11:30:07 -08:00
Wesley W. Terpstra	179c93db42	tilelink2 broadcast: make it controlled via Config	2016-11-17 17:26:49 -08:00
Wesley W. Terpstra	f4ca5ea1f3	rocketchip: match simulated memory width to ExtMem.beatBytes	2016-11-17 15:40:47 -08:00
Wesley W. Terpstra	12d0d8bea2	rocketchip: remove obsolete bus configuration	2016-11-17 14:30:15 -08:00
Wesley W. Terpstra	c82b371354	rocketchip: remove obsolete TL1 config	2016-11-17 14:24:45 -08:00
Wesley W. Terpstra	dfc3a0dafb	tilelink2: do not depend on obsolete TL1 configuration	2016-11-17 14:07:53 -08:00
Henry Cook	84f249bd03	[rocketchip] BigInt cast	2016-11-16 18:11:06 -08:00
Henry Cook	408e78e35e	rocketchip Periphery: ExtMem and ExtBus Configs	2016-11-16 16:50:30 -08:00
Wesley W. Terpstra	10e459fedb	rocket: change connection between rocketchip and coreplex ... * rtc and dtm are now crossed half-and-half on the two sides * groundtest no longer uses riscv platform traits	2016-11-15 18:27:52 -08:00
Wesley W. Terpstra	385b5d5698	axi4: default should be GET_EFFECTS	2016-11-14 15:19:39 -08:00
Wesley W. Terpstra	32fd11935c	rocketchip: use TL2 and AXI4 for memory subsytem	2016-11-04 13:36:47 -07:00
Wesley W. Terpstra	f943c5d6ef	rocketchip: connect rtcTick to coreplex	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	aabd17d935	rocketchip: must create bundles within Module scope ... 1. Bundles be created after base class Module constructor runs 2. Bundles must be created before Module(...) runs Solution: pass a bundle constructor to the cake base class Require the constructor to take a parameter so people don't use it by accident; they should get a type error. Consistently name all the cake arguments with an _io, _coreplex, _outer, so that they don't shadow the base class variables you should be using.	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	4de1822470	rocketchip: avoid using the nearly defunct GlobalAddrMap	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	688e1bffdf	rocketchip: pull rtcTick out of the coreplex	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	5bca13ebdb	rocketchip: use self-type constraints	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	d51b0b5c02	rocketchip: use self-type	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	ba529c3716	rocketchip: use TileLink2 interrupts	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	ac886026e6	rocketchip: reduce number of type parameters	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	72a7948ad2	rocketchip Periphery: move atomics before WidthWidget => 64-bit AMOs	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	e9725aea2f	rocketchip: all of the address map now comes from TL2	2016-10-31 11:42:44 -07:00
Wesley W. Terpstra	401fd378b4	rocketchip: include devices from cbus in ConfigString	2016-10-31 11:42:13 -07:00
Wesley W. Terpstra	a73aa351ca	rocketchip: fix all clock crossings	2016-10-31 11:42:13 -07:00
Wesley W. Terpstra	825c253a72	rocketchip: move TL2 and cake pattern into Coreplex	2016-10-31 11:42:13 -07:00
Wesley W. Terpstra	89139a9492	Plic: split constants from variables used in config string	2016-10-31 11:42:13 -07:00
Wesley W. Terpstra	f8a0829134	rocketchip: remove clint; it moves into coreplex	2016-10-31 11:42:13 -07:00
Wesley W. Terpstra	c3dacca39a	rocketchip: remove pbus; TL2 has swallowed it completely	2016-10-31 11:42:08 -07:00
Wesley W. Terpstra	3df797fcab	rocketchip: replace TL1 MMIO with an example of TL2 MMIO	2016-10-31 11:41:18 -07:00
Wesley W. Terpstra	ec2d23b8b7	rocketchip: Bundle-slices need access to the outer LazyModule ... We need this change in order for some ports to use parameters that result from LazyModule diplomacy. Now you can eat your cake too!	2016-10-31 11:41:18 -07:00
Wesley W. Terpstra	0ae45d0f24	rocketchip: bundle (=> B) need not be delayed; Module is constructed later	2016-10-31 11:41:18 -07:00
Wesley W. Terpstra	0dbda2f07d	rocketchip: remove obsolete pDevices used during TL1=>2 migration	2016-10-31 11:41:18 -07:00
Wesley W. Terpstra	67ab27f5a5	diplomacy: guess the LazyModule name from the containing class	2016-10-25 15:58:09 -07:00
Wesley W. Terpstra	7dc97674d6	rocketchip: include an socBus between l1tol2 and periphery (#415) ... Sometimes we have high performance devices that go inbetween.	2016-10-24 23:56:09 -07:00