Wesley W. Terpstra 10e459fedb rocket: change connection between rocketchip and coreplex ... * rtc and dtm are now crossed half-and-half on the two sides * groundtest no longer uses riscv platform traits		2016-11-15 18:27:52 -08:00
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BaseTop.scala	rocket: change connection between rocketchip and coreplex	2016-11-15 18:27:52 -08:00
Configs.scala	rocket: change connection between rocketchip and coreplex	2016-11-15 18:27:52 -08:00
DebugTransport.scala	rocket: change connection between rocketchip and coreplex	2016-11-15 18:27:52 -08:00
ExampleTop.scala	rocket: change connection between rocketchip and coreplex	2016-11-15 18:27:52 -08:00
Generator.scala	rocketchip: generate GraphML output	2016-09-26 14:35:46 -07:00
Periphery.scala	rocket: change connection between rocketchip and coreplex	2016-11-15 18:27:52 -08:00
RISCVPlatform.scala	rocket: change connection between rocketchip and coreplex	2016-11-15 18:27:52 -08:00
RocketTestSuite.scala	fix typo rv64iu -> rv64ui	2016-09-22 17:33:35 -07:00
TestHarness.scala	rocket: change connection between rocketchip and coreplex	2016-11-15 18:27:52 -08:00
Utils.scala	rocketchip: use TL2 and AXI4 for memory subsytem	2016-11-04 13:36:47 -07:00