1
0
Commit Graph

5015 Commits

Author SHA1 Message Date
Wesley W. Terpstra
0dbda2f07d rocketchip: remove obsolete pDevices used during TL1=>2 migration 2016-10-31 11:41:18 -07:00
Megan Wachs
af924d8c51 DebugModule: Instantiate TL2 DebugModule in BaseCoreplex 2016-10-31 11:41:18 -07:00
Megan Wachs
d530ef7236 DebugModule: translate to TL2 with {32,64}-bit XLen width 2016-10-31 11:41:18 -07:00
Howard Mao
3e08d615f0 Merge pull request #427 from ucb-bar/put-after-release-bugfix
Fix issue with PutBlock and Release in BroadcastHub
2016-10-31 11:28:24 -07:00
Howard Mao
f0e9a2a081 Fix PutBlock after Release bug
There is logic in the broadcast hub to skip the outer acquire if there
is an outgoing release, since the data will be written out through the
release channel. However, this will cause an issue in the case of
PutBlock requests. If the tail beats of the PutBlock show up after the
outer release has already been sent, the data will be corrupted.

The fix is to make the outer release block if there are pending
inner PutBlock beats.
2016-10-28 18:26:34 -07:00
Howard Mao
cb81ea516c add regression test for put-after-release bug 2016-10-28 18:26:34 -07:00
Howard Mao
fa8844d5c3 properly use rocket MT_ constants in regression tests 2016-10-28 18:26:34 -07:00
Andrew Waterman
f8bb67ab8f Bind some Make vars early to avoid redundant evaluation 2016-10-28 11:56:13 -07:00
Andrew Waterman
f3c726033a Make all Chisel invocations depend on FIRRTL_JAR 2016-10-28 11:56:05 -07:00
Andrew Waterman
2b65478f3a bump chisel/firrtl 2016-10-28 00:36:53 -07:00
Andrew Waterman
e45b41b4b6 Don't rely on SeqMem output after read-enable is low 2016-10-27 23:44:10 -07:00
Andrew Waterman
190a8b9dd3 Update README.md to reflect firrtl and riscv-tools changes 2016-10-27 11:40:09 -07:00
Richard Xia
8c538f548b Merge pull request #422 from ucb-bar/use-random-port-for-jtag-vpi
Use random, unused port for JTAG VPI
2016-10-26 13:16:28 -07:00
Richard Xia
cc5b7d1eb6 Bump riscv-tools. 2016-10-26 11:40:49 -07:00
Richard Xia
183ae58704 Use a random port number for JTAG VPI. 2016-10-26 11:40:45 -07:00
Howard Mao
900a7bbcf1 add PutAtomic support to width adapter 2016-10-26 09:58:26 -07:00
Jacob Chang
47887c40ac Merge pull request #421 from ucb-bar/fix_async_fifo
Fixed AsyncFifo with reset messaging
2016-10-25 18:22:27 -07:00
Jacob Chang
fc5eb7cc64 Fixed AsyncFifo with reset messaging 2016-10-25 16:45:08 -07:00
Megan Wachs
fd2d48acda lazy_module: If the user actually specifies a name, just use it without appending module name. 2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
a807c922d0 diplomacy: take names from the outermost common node 2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
fee67c4abf diplomacy: add methods to find {out,in}ner-most common node 2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
67ab27f5a5 diplomacy: guess the LazyModule name from the containing class 2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
4d50733548 tilelink2 ToAXI4: use helper method for a_last (#418) 2016-10-25 10:16:42 -07:00
Wesley W. Terpstra
7dc97674d6 rocketchip: include an socBus between l1tol2 and periphery (#415)
Sometimes we have high performance devices that go inbetween.
2016-10-24 23:56:09 -07:00
Wesley W. Terpstra
a5ac106bb8 axi4 ToTL: fix decode error arbitration (#417)
When selecting between error generation on R and real data on R,
correctly calculate the R backpressure.

This bug manifests when a valid request is immediately followed by
an invalid request, wedging the R channel.
2016-10-24 22:15:19 -07:00
Wesley W. Terpstra
4c815f7958 tilelink2 Parameters: fix {contains,supports}Safe (#416)
When there is only one manager, you still want to know if the address
was wrong on the link to that manager!
2016-10-24 20:37:04 -07:00
Scott Johnson
b9a082223c Merge pull request #414 from ucb-bar/sanity-check-debug
Sanity check compile-time vs simulation-time options
2016-10-24 15:58:29 -07:00
Scott Johnson
f382ee70da Sanity check compile-time vs simulation-time options
If user compiles without +define+DEBUG but then requests +vcdfile at
simulation time, that request would be silently ignored. This changes
it to a fatal error.

It's good philosophy to treat plusargs like +vcdfile as commands, not
suggestions, and die immediately if they cannot be honored, instead of
silently ignoring them. Otherwise the user sits through the entire
simulation and then is left scratching his head wondering where his
waveforms are.
2016-10-24 14:45:34 -07:00
Colin Schmidt
737cf82478 Print out seed if we can (#412)
Now that we have ifdef VCS in here lets use it for something more than compatibility
2016-10-24 12:36:29 -07:00
Scott Johnson
bc01f85164 Merge pull request #406 from ucb-bar/incisive-fixes
More Cadence Incisive fixes
2016-10-24 10:48:24 -07:00
Andrew Waterman
9326cfd64a Merge branch 'master' into incisive-fixes 2016-10-23 23:08:01 -07:00
Jack Koenig
288d7169ae Bump firrtl and update vsim Makefrag-verilog (#409) 2016-10-23 23:07:47 -07:00
Wesley W. Terpstra
8bfd6bcd4d axi4: ensure we accept AR before reporting R (#411) 2016-10-21 21:02:05 -07:00
Colin Schmidt
cb8878c931 Don't build any hurricane branches
Don't mean to eat up travis bandwidth but shared branches sometimes get made.
2016-10-21 16:26:41 -07:00
Colin Schmidt
85f3788ab5 initialize s2_hit to solve #401 2016-10-21 14:53:55 -07:00
Scott Johnson
a919a280e8 Fix Cadence Incisive compile errors; VCD-Plus is a VCS-only format
This fixes the following compile warnings and simulation errors:

Compile-time warnings:
      $vcdplusfile(vcdplusfile);
                 |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): Unrecognized system task or function: $vcdplusfile (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
      $vcdpluson(0);
               |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): Unrecognized system task or function: $vcdpluson (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
      $vcdplusmemon(0);
                  |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): Unrecognized system task or function: $vcdplusmemon (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
        `VCDPLUSCLOSE
                    |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): Unrecognized system task or function: $vcdplusclose (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].

Which then become simulation-time errors:

      $vcdplusfile(vcdplusfile);
                 |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): User Defined system task or function ($vcdplusfile) registered during elaboration and used within the simulation has not been registered during simulation.
      $vcdpluson(0);
               |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): User Defined system task or function ($vcdpluson) registered during elaboration and used within the simulation has not been registered during simulation.
      $vcdplusmemon(0);
                  |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): User Defined system task or function ($vcdplusmemon) registered during elaboration and used within the simulation has not been registered during simulation.
        `VCDPLUSCLOSE
                    |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
        `VCDPLUSCLOSE
                    |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,97|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
2016-10-19 13:26:31 -07:00
Scott Johnson
9f0fda01b3 Fix Cadence Incisive compile warning
The SystemVerilog LRM (IEEE 1800-2012) clause 20.15.1 ($random
function) says: "The seed argument shall be an integral variable."

This fixes the following compile warning:

    rand_value = $random($urandom);
                       |
ncelab: *W,WRNOTL (/home/scottj/rocket-chip/vsrc/TestDriver.v,34|23): Argument to out parameter is not a legal lvalue.
2016-10-19 13:23:36 -07:00
Scott Johnson
f069052969 Merge pull request #403 from ucb-bar/fix-incisive-warning
Fix Verilog compile warning from Cadence Incisive
2016-10-18 10:48:32 -07:00
Scott Johnson
dc4c375c7f Silence Verilog compile warning from Cadence Incisive 2016-10-17 15:44:24 -07:00
Wesley W. Terpstra
c8fc05d154 Merge pull request #402 from ucb-bar/axi4-slave
AXI4=>TL2 converter
2016-10-17 10:34:29 -07:00
Wesley W. Terpstra
7c334e3c34 axi4 ToTL: shorter critical path on Q.bits if errors go first 2016-10-17 01:00:49 -07:00
Wesley W. Terpstra
73010c79a3 axi4 ToTL: handle bad AXI addresses 2016-10-17 00:12:26 -07:00
Wesley W. Terpstra
501d6d689f axi4: Test ToTL 2016-10-16 22:04:06 -07:00
Wesley W. Terpstra
5a1da63b5a axi4: prototype ToTL adapter 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
72e5a97d40 tilelink2: factor out the OH1ToOH function 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
d09f43c32f axi4 Bundles: add a size calculation helper
The old version was wrong.
Inverting before the << has a different width.
This means you end up with high bits set.
2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
ee66fd28eb Merge pull request #400 from ucb-bar/better-crossing-asserts
Better crossing reset handling
2016-10-14 19:19:37 -07:00
Wesley W. Terpstra
20288729b9 tilelink2 Isolation: cross the valid signals as well
Refactor the code to be less copy-pasty
2016-10-14 18:28:36 -07:00
Wesley W. Terpstra
680a944f07 regmapper RegisterCrossing: safe AsyncQueues are overkill here 2016-10-14 18:28:31 -07:00
Wesley W. Terpstra
ac0bb841da AsyncQueue: cope with far reset propagation delay 2016-10-14 18:05:35 -07:00