d52615c39e
coreplex: one IntNode per tile
2016-10-31 11:42:47 -07:00
e97844f71e
coreplex: make it possible to override the ConfigString
2016-10-31 11:42:47 -07:00
688e1bffdf
rocketchip: pull rtcTick out of the coreplex
2016-10-31 11:42:47 -07:00
d51b0b5c02
rocketchip: use self-type
2016-10-31 11:42:47 -07:00
841a31479a
coreplex: fix TinyConfig
2016-10-31 11:42:47 -07:00
ba529c3716
rocketchip: use TileLink2 interrupts
2016-10-31 11:42:47 -07:00
6505431eac
coreplex: use self-type constraints
2016-10-31 11:42:47 -07:00
ac886026e6
rocketchip: reduce number of type parameters
2016-10-31 11:42:47 -07:00
401fd378b4
rocketchip: include devices from cbus in ConfigString
2016-10-31 11:42:13 -07:00
a73aa351ca
rocketchip: fix all clock crossings
2016-10-31 11:42:13 -07:00
825c253a72
rocketchip: move TL2 and cake pattern into Coreplex
2016-10-31 11:42:13 -07:00
dddb50a942
BuildTiles: convert to LazyTile
2016-10-31 11:42:13 -07:00
b99662796d
PLIC: converted to TL2
2016-10-31 11:42:13 -07:00
bddfa4d69b
Debug: make address configurable
2016-10-31 11:42:13 -07:00
c3dacca39a
rocketchip: remove pbus; TL2 has swallowed it completely
2016-10-31 11:42:08 -07:00
0ae45d0f24
rocketchip: bundle (=> B) need not be delayed; Module is constructed later
2016-10-31 11:41:18 -07:00
af924d8c51
DebugModule: Instantiate TL2 DebugModule in BaseCoreplex
2016-10-31 11:41:18 -07:00
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
968851f7e3
Default to configurable priorities
...
up-to-7 levels is kind of arbitrary, but I'm unwilling to introduce
a new Parameter at the moment.
2016-10-04 22:29:39 -07:00
f05298d9bc
tilelink2: move general-purpose code out of tilelink2 package
2016-10-03 16:22:28 -07:00
ab3219cf6e
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
c45cc76cef
Get rid of remaining MemIO code
...
The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.
2016-09-27 16:28:17 -07:00
7d6fb950b6
Give TileLink IDs more sensible names
...
* Outermost -> MCtoEdge
* MMIO_Outermost -> MMIOtoEdge
Then the corresponding parameters objects are
* L1toL2 -> innerParams
* L2toMC -> outerMemParams
* L2toMMIO -> outerMMIOParams
* MCtoEdge -> edgeMemParams
* MMIOtoEdge -> edgeMMIOParams
2016-09-27 12:48:01 -07:00
8a55521b01
move memory width adapter from coreplex to periphery
2016-09-27 12:48:01 -07:00
201e247f73
Factor coreplex IO connection into separate trait ( #350 )
...
This would allow, for instance, putting the coreplex on a separate clock
domain and crossing the IOs over through asynchronous queues.
The ExampleMultiClockTop* classes are removed since they no longer fit
into the class hierarchy.
2016-09-27 11:55:32 -07:00
ea9f0a868f
TileLink utility objects should not take implicit parameters
...
We have a handful of TileLink-related helper objects
(wrappers, unwrappers, width adapters, and enqueuers). Previously, using
them could be error-prone, because you had to make sure the implicit
parameters they took in had the same TLId as the TileLinkIO bundles
passed in as inputs. This is rather silly, we should just use the
parameters in the bundle.
2016-09-26 17:28:21 -07:00
803739a95c
Make sure coreplex mmio's TLId is correct (thanks to zizztux)
2016-09-26 17:28:21 -07:00
1b1ef3be07
simplify base Coreplex bundle
2016-09-21 18:29:28 -07:00
5bb575ef74
rename internal/external MMIO network to cbus/pbus respectively
2016-09-21 18:29:28 -07:00
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
