237 lines
8.6 KiB
Scala
237 lines
8.6 KiB
Scala
package coreplex
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import diplomacy._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.util._
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import uncore.converters._
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import rocket._
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import util._
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/** Number of memory channels */
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case object NMemoryChannels extends Field[Int]
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/** Number of banks per memory channel */
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case object NBanksPerMemoryChannel extends Field[Int]
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/** Least significant bit of address used for bank partitioning */
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case object BankIdLSB extends Field[Int]
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/** Function for building some kind of coherence manager agent */
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case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
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/** Function for building some kind of tile connected to a reset signal */
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case object BuildTiles extends Field[Seq[Parameters => LazyTile]]
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/** The file to read the BootROM contents from */
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case object BootROMFile extends Field[String]
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trait HasCoreplexParameters {
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implicit val p: Parameters
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lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
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lazy val lsb = p(BankIdLSB)
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lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
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lazy val outerMemParams = p.alterPartial({ case TLId => "L2toMC" })
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lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
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lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
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lazy val nTiles = p(uncore.devices.NTiles)
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lazy val nSlaves = p(rocketchip.NCoreplexExtClients)
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lazy val nMemChannels = p(NMemoryChannels)
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lazy val hasSupervisor = p(rocket.UseVM)
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}
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case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters
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abstract class BareCoreplex(implicit val p: Parameters) extends LazyModule
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abstract class BareCoreplexBundle[+L <: BareCoreplex](val outer: L) extends Bundle
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abstract class BareCoreplexModule[+B <: BareCoreplexBundle[BareCoreplex]](val io: B) extends LazyModuleImp(io.outer) {
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val outer = io.outer.asInstanceOf[io.outer.type]
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}
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trait CoreplexNetwork extends HasCoreplexParameters {
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this: BareCoreplex =>
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val l1tol2 = LazyModule(new TLXbar)
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val l1tol2_beatBytes = p(TLKey("L2toMMIO")).dataBitsPerBeat/8
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val l1tol2_lineBytes = p(CacheBlockBytes)
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val cbus = LazyModule(new TLXbar)
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val cbus_beatBytes = p(XLen)/8
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val cbus_lineBytes = l1tol2_lineBytes
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val mmio = TLOutputNode()
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val mmioInt = IntInputNode()
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cbus.node :=
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TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
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TLWidthWidget(l1tol2_beatBytes)(
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TLBuffer()(
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l1tol2.node)))
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mmio :=
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TLBuffer()(
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TLWidthWidget(l1tol2_beatBytes)(
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l1tol2.node))
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}
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trait CoreplexNetworkBundle extends HasCoreplexParameters {
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this: {
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val outer: CoreplexNetwork
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} =>
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implicit val p = outer.p
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val mmio = outer.mmio.bundleOut
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val interrupts = outer.mmioInt.bundleIn
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}
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trait CoreplexNetworkModule extends HasCoreplexParameters {
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this: BareCoreplexModule[BareCoreplexBundle[BareCoreplex]] =>
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implicit val p = outer.p
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}
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trait CoreplexRISCV {
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this: CoreplexNetwork =>
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// Build a set of Tiles
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val lazyTiles = p(BuildTiles) map { _(p) }
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val legacy = LazyModule(new TLLegacy()(outerMMIOParams))
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val tileIntNode = IntInternalOutputNode() // this should be moved into the Tile...
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val debug = LazyModule(new TLDebugModule())
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val plic = LazyModule(new TLPLIC(hasSupervisor, maxPriorities = 7))
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val clint = LazyModule(new CoreplexLocalInterrupter)
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// Kill this once we move TL2 into rocket
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l1tol2.node :=
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TLHintHandler()(
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legacy.node)
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debug.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
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plic.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
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clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
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plic.intnode := mmioInt
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lazyTiles.foreach { _ => tileIntNode := plic.intnode }
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}
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trait CoreplexRISCVBundle {
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this: CoreplexNetworkBundle {
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val outer: CoreplexRISCV
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} =>
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val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outerMemParams))
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val slave = Vec(nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
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val resetVector = UInt(INPUT, p(XLen))
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val success = Bool(OUTPUT) // used for testing
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val debug = new DebugBusIO().flip
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}
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trait CoreplexRISCVModule {
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this: CoreplexNetworkModule {
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val outer: CoreplexNetwork with CoreplexRISCV
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val io: CoreplexRISCVBundle
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} =>
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val tiles = outer.lazyTiles.map(_.module)
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val uncoreTileIOs = (tiles zipWithIndex) map { case (tile, i) => Wire(tile.io) }
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println("\nGenerated Address Map")
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for (entry <- p(rocketchip.GlobalAddrMap).flatten) {
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val name = entry.name
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val start = entry.region.start
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val end = entry.region.start + entry.region.size - 1
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val prot = entry.region.attr.prot
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val protStr = (if ((prot & AddrMapProt.R) > 0) "R" else "") +
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(if ((prot & AddrMapProt.W) > 0) "W" else "") +
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(if ((prot & AddrMapProt.X) > 0) "X" else "")
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val cacheable = if (entry.region.attr.cacheable) " [C]" else ""
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println(f"\t$name%s $start%x - $end%x, $protStr$cacheable")
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}
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// Create and export the ConfigString
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val managers = outer.l1tol2.node.edgesIn(0).manager.managers
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val configString = rocketchip.GenerateConfigString(p, outer.clint, outer.plic, managers)
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println(s"\nGenerated Configuration String\n${configString}")
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ConfigStringOutput.contents = Some(configString)
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val nCachedPorts = tiles.map(tile => tile.io.cached.size).reduce(_ + _)
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val nUncachedPorts = tiles.map(tile => tile.io.uncached.size).reduce(_ + _)
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val nBanks = nMemChannels * nBanksPerMemChannel
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buildUncore(p.alterPartial({
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case HastiId => "TL"
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case TLId => "L1toL2"
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case NCachedTileLinkPorts => nCachedPorts
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case NUncachedTileLinkPorts => nUncachedPorts
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}))
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def buildUncore(implicit p: Parameters) {
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// Create a simple L1toL2 NoC between the tiles and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: UInt): UInt = if (nBanks == 0) UInt(0) else {
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val isMemory = globalAddrMap.isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
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Mux(isMemory, addr.extract(lsb + log2Ceil(nBanks) - 1, lsb), UInt(nBanks))
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}
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val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId))
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// Create point(s) of coherence serialization
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val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)}
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managerEndpoints.flatMap(_.incoherent).foreach(_ := Bool(false))
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val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({
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case TLId => "L1toL2"
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMMIO"
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})))
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// Wire the tiles to the TileLink client ports of the L1toL2 network,
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// and coherence manager(s) to the other side
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l1tol2net.io.clients_cached <> uncoreTileIOs.map(_.cached).flatten
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l1tol2net.io.clients_uncached <> uncoreTileIOs.map(_.uncached).flatten ++ io.slave
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
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outer.legacy.module.io.legacy <> mmioManager.io.outer
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val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outerMemParams))
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
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val enqueued = TileLinkEnqueuer(bank.outerTL, backendBuffering)
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icPort <> TileLinkIOUnwrapper(enqueued)
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}
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io.mem <> mem_ic.io.out
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}
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// connect coreplex-internal interrupts to tiles
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for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
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tile.hartid := UInt(i)
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tile.resetVector := io.resetVector
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tile.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
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tile.interrupts.meip := outer.tileIntNode.bundleOut(i)(0)
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tile.interrupts.seip.foreach(_ := outer.tileIntNode.bundleOut(i)(1))
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}
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outer.debug.module.io.db <> io.debug
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outer.clint.module.io.rtcTick := Counter(p(rocketchip.RTCPeriod)).inc()
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// Coreplex doesn't know when to stop running
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io.success := Bool(false)
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}
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class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
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with CoreplexNetwork
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with CoreplexRISCV {
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override lazy val module = new BaseCoreplexModule(new BaseCoreplexBundle(this))
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}
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class BaseCoreplexBundle[+L <: BaseCoreplex](outer: L) extends BareCoreplexBundle(outer)
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with CoreplexNetworkBundle
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with CoreplexRISCVBundle
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class BaseCoreplexModule[+B <: BaseCoreplexBundle[BaseCoreplex]](io: B) extends BareCoreplexModule(io)
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with CoreplexNetworkModule
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with CoreplexRISCVModule
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