riscv/rocket-chip
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d3ccec1044
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44 Commits

Author SHA1 Message Date
Henry Cook
d3ccec1044 Massive update containing several months of changes from the now-defunct private chip repo. 
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
 2015-07-02 14:43:30 -07:00
Amirali Sharifian
879a4a0bcd Update Makefile 
Change default shell to bash shell.
 2015-04-06 15:05:43 -07:00
Adam Izraelevitz
484648d9c7 Changed CONFIG from a recursively expanded variable to a conditionally 
assigned variable, allowing users to define CONFIG external to Makefile
 2014-09-17 11:12:02 -07:00
Yunsup Lee
275b72368b add CONFIG to the name of simulator executable 2014-09-11 22:11:58 -07:00
Yunsup Lee
cfecd8832d tease out reference-chip specific stuff 2014-09-09 20:49:28 -07:00
Henry Cook
82467313dd merge in rocketchip changes from master 2014-09-02 13:51:57 -07:00
Yunsup Lee
c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00
Henry Cook
0ca24a5d91 fix debug flags 2014-08-12 10:35:39 -07:00
Adam Izraelevitz
08d81d0892 First cut at using new chisel parameters for toplevel parameters and fpu 2014-08-01 18:09:37 -07:00
Stephen Twigg
6808245bb5 Timeout cycles now defined in toplevel Makefrag in order to allow for easier alteration when debugging. 2014-02-12 16:50:13 -08:00
Christopher Celio
fc52840ce2 move timeout in Makefile to a variable 2014-01-31 16:52:59 -08:00
Andrew Waterman
e9d3a650a4 Speed up C++ compilation 2014-01-31 12:25:19 -08:00
Andrew Waterman
fb827abbfa Use dynamic fesvr library 2014-01-28 03:50:19 -08:00
Andrew Waterman
8c380a7c3a Abort "make run" when tests fail 2013-10-29 13:25:57 -07:00
Andrew Waterman
b7d7ced41b Update to new ISA 2013-09-21 06:40:23 -07:00
Andrew Waterman
628745226c Use spike disassembler riscv-dis if it exists 2013-09-15 04:25:53 -07:00
Andrew Waterman
fbdbb01232 update to new isa; disable vector tests 2013-09-12 17:04:03 -07:00
Henry Cook
6aa500fc16 dont make assumptions about default project name when invoking sbt 2013-08-20 12:56:01 -07:00
Henry Cook
b06d33da2f Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes 2013-08-19 19:54:41 -07:00
Henry Cook
85e5ce046f pulled submodule commits, uncore sbt standardized 2013-08-15 17:07:13 -07:00
Andrew Waterman
4ae0c68303 require -std=c++11, as -std=c++0x doesn't cut it 2013-06-14 00:28:42 -07:00
Henry Cook
896179cbb6 removed bad mt test 2013-06-14 00:14:18 -07:00
Henry Cook
85fbb650c9 makefile support for new multithreading tests 2013-06-13 15:34:54 -07:00
Yunsup Lee
a86ad08c1e commit awesome vlsi/energy scripts 2013-05-01 02:59:11 -07:00
Yunsup Lee
9114012def assmebly tests are now built from riscv-tests 2013-04-24 01:59:14 -07:00
Henry Cook
c6b56c5f25 bump rocket for coherence bug fix 2013-04-04 15:52:20 -07:00
Andrew Waterman
def11e44b8 don't pipe stdout to vcd2vpd 2013-03-25 17:01:13 -07:00
Andrew Waterman
ef4927c9ad use a named pipe for VCD -> VPD conversion 2013-03-25 16:19:19 -07:00
Andrew Waterman
dbb61306f0 randomize coreid mapping 2013-01-26 16:13:14 -08:00
Andrew Waterman
4077b22929 include fesvr as a library; improve harnesses 2013-01-24 23:57:23 -08:00
Yunsup Lee
217898c7d0 emulator depends on source files in src directory 2013-01-23 01:39:47 -08:00
Andrew Waterman
d911e635d6 simplify c++ memory models; support +dramsim flag 
works for both vlsi and emulator
 2012-12-04 07:04:26 -08:00
Andrew Waterman
e12af07722 update to newest rocket 2012-11-25 04:40:46 -08:00
Andrew Waterman
6d47d18c2b catch sigterm to gracefully exit (fixes vcd) 2012-11-20 05:40:44 -08:00
Andrew Waterman
7bcf59a18f support continous compilation via "make test" 
for c++ emulator only, for now
 2012-11-17 19:58:18 -08:00
Yunsup Lee
dd6ee2571d add vector vm tests 2012-11-04 19:29:56 -08:00
Andrew Waterman
4ed2d614a2 update to new rocket; retime fpu in dc-syn 2012-11-04 16:43:02 -08:00
Henry Cook
538b23c223 Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles 2012-10-23 12:52:59 -07:00
Andrew Waterman
367b5489d1 first crack at continuous compilation/testing flow 
try it out: cd emulator; make test
 2012-10-19 04:09:07 -07:00
Andrew Waterman
1ad928cfe2 directly integrate dramsim build 
also, build it as a static library to simplify dependencies
 2012-10-18 18:59:37 -07:00
Andrew Waterman
edf0eeed01 integrate updated rocket/uncore 2012-10-18 17:51:41 -07:00
Miquel Moreto
6d49dc51a0 Fixed emulator Makefile + extra info in the README file 2012-10-16 11:06:48 -07:00
Miquel Moreto
5d75ddc553 Added dramsim2 memory model to the emulator backend 2012-10-14 14:06:28 -07:00
Huy Vo
93a0182b96 everything to get emulator working 2012-10-01 19:30:11 -07:00