30c8c8c517
Revert "try to give seqmems clearer names"
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This reverts commit 8db5bbbae0
2017-09-21 18:02:32 -07:00
e0b9f9213a
make halt_and_catch_fire Optional
2017-09-21 14:58:47 -07:00
28b635e721
tile: add halt_and_catch_fire signal
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for unrecoverable / fatal errors
2017-09-21 14:58:47 -07:00
a887baa615
rocket: base trait for reporting ecc errors
2017-09-21 14:58:47 -07:00
ffa3ab29ac
Merge pull request #1006 from freechipsproject/async_reset_reg
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async_reset_reg: Don't randomize the register if rst is asserted anyway
2017-09-21 11:48:04 -07:00
4f58aab26f
Bumpplugins - add sbt-coverage ( #1004 )
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Don't advance to plugin versions that are incompatible with current chisel3 code.
2017-09-20 17:17:55 -07:00
88c782cc70
Report D$ uncorrectable errors on C channel
2017-09-20 17:15:11 -07:00
6bc20942b5
Don't cache TL error responses; report access exceptions
2017-09-20 17:01:08 -07:00
323a207bdd
Merge pull request #1005 from freechipsproject/trace
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Rename trace.addr -> iaddr
2017-09-20 15:34:45 -07:00
9b828a2640
Only look at error signal on last beat
2017-09-20 15:15:21 -07:00
cda89fbacb
async_reset_reg: Don't randomize the register if rst is asserted anyway
2017-09-20 14:47:00 -07:00
026fa14bf8
Rename trace.addr -> iaddr
2017-09-20 14:32:41 -07:00
1cb91eed41
Merge pull request #1003 from freechipsproject/ma-fetch
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Don't write badaddr on misaligned fetch exceptions
2017-09-20 14:28:26 -07:00
5b2f458214
Merge branch 'master' into ma-fetch
2017-09-20 12:18:03 -07:00
f1a506476b
Merge pull request #994 from freechipsproject/beu
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Add L1 bus-error unit
2017-09-20 12:17:08 -07:00
00cf089350
Merge pull request #1002 from freechipsproject/trace
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Add instruction-trace port
2017-09-20 11:50:40 -07:00
f5bd639863
Don't write badaddr on misaligned fetch exceptions
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It's optional, and we were doing it wrong before, so just don't do it.
2017-09-20 10:52:41 -07:00
db57e943f3
Report TL errors into D$
2017-09-20 00:05:07 -07:00
aaad73f019
Add an intra-tile xbar
2017-09-20 00:05:07 -07:00
afad25fceb
Integrate L1 BusErrorUnit
2017-09-20 00:05:07 -07:00
dbf599f6a1
Support SynchronizerShiftReg(sync = 0)
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This makes it easier to parameterize code where the synchronizer
might not always be needed.
2017-09-20 00:05:07 -07:00
79dab487fc
Implement bus error unit
2017-09-20 00:05:07 -07:00
ed18acaae0
Report D$ errors
2017-09-20 00:05:07 -07:00
034ea722f4
Report I$ errors
2017-09-20 00:05:07 -07:00
9a175b0fb1
Statically report error correction/detection capability from ECC codes
2017-09-20 00:05:07 -07:00
4d6d6ff641
Add instruction-trace port
2017-09-19 22:59:57 -07:00
acea94bcef
Merge pull request #1001 from freechipsproject/address-decoder
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Address decoder "improvements"
2017-09-19 22:38:53 -07:00
b4fc5104d4
Add cover property API that can be refined through Config PropertyLibrary ( #998 )
2017-09-19 19:26:54 -07:00
57e8fe0a6b
Merge pull request #1000 from freechipsproject/name-seqmems
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try to give seqmems clearer names for use with external tools
2017-09-19 17:59:00 -07:00
87b92cb206
Scan AddressDecoder bits left to right
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This heuristic is brittle but fixes deduplication in RocketTile.
2017-09-19 17:47:24 -07:00
72bd89a2af
Add another AddressDecoder debug message
2017-09-19 17:47:17 -07:00
fb2ad11347
Improve AddressDecoder optimization function
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This function is better 27% of the time but worse 6% of the time.
2017-09-19 17:47:12 -07:00
8db5bbbae0
try to give seqmems clearer names
2017-09-19 13:41:11 -07:00
cbd65cd247
Merge pull request #992 from freechipsproject/test_mode_reset
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reset_catch: Allow Test Mode Overrides
2017-09-18 14:16:49 -07:00
528deefdc7
Change SystemVerilog statement into standard Verilog ( #997 )
2017-09-18 10:57:07 -07:00
826fc8ba61
Merge remote-tracking branch 'origin/master' into test_mode_reset
2017-09-18 09:50:27 -07:00
c24b275fd9
Merge pull request #996 from freechipsproject/fix-dcache-bug
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Only merge stores that aren't yet pending
2017-09-17 15:59:32 -07:00
d93d7b9fa4
Only merge stores that aren't yet pending
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This fixes a deadlock (and possibly memory corruption, though that is
unconfirmed). The following sequence manifests it, assuming t0
is 32-byte aligned:
sw t0, 0(t0)
sw t0, 16(t0)
lw t1, 4(t0)
lw t2, 4(t0)
2017-09-17 15:01:07 -07:00
c85333f826
Merge remote-tracking branch 'origin/test_mode_reset' into test_mode_reset
2017-09-17 13:51:46 -07:00
215e072e5c
test_mode_reset: fix typos
2017-09-17 13:51:40 -07:00
9b75dd7e5b
Merge branch 'master' into test_mode_reset
2017-09-15 17:26:11 -07:00
641a8e7eab
test_mode_reset: Correct some gender issues. Tie off signals in the test harness
2017-09-15 16:36:35 -07:00
e8702e2687
Merge pull request #989 from freechipsproject/config-cleanups
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Clean up various Configs/Fields/Params
2017-09-15 13:45:15 -07:00
6cda4504ac
test_mode_reset: use a cleaner interface with bundles and options instead of individual signals
2017-09-15 12:30:39 -07:00
ffc514d1bc
test_mode_reset: Add missing file
2017-09-14 13:17:37 -07:00
a0396b63e8
test_mode_reset: fix one bulk-connect gender issue
2017-09-14 13:16:13 -07:00
44edc5fdc3
test_mode_reset: Use simpler apply() method
2017-09-14 13:16:13 -07:00
82c00cb656
reset_catch: Allow Test Mode Overrides
2017-09-14 13:16:13 -07:00
e50d14415e
tilelink: more verbose requires
2017-09-13 11:25:42 -07:00
56dae946b6
coreplex: MemoryBusParams.beatBytes also based on XLen
2017-09-13 11:25:42 -07:00
