riscv/rocket-chip
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599 Commits

Author SHA1 Message Date
Wesley W. Terpstra
e0741a2097 axi4: don't map unused masters into TL source ID space 2017-06-02 16:30:16 -07:00
Wesley W. Terpstra
d25ad10592 diplomacy: require masters to have a name 2017-06-02 15:52:20 -07:00
Wesley W. Terpstra
ae8734da05 diplomacy: report cacheability in ResourceAddress 2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
985d9750e6 tilelink2: Xbar QoR improvement 2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
9317a00896 tilelink2: ToAXI4, sort and print AXI IDs used 2017-06-02 14:27:37 -07:00
Wesley W. Terpstra
eb14329c63 tilelink2: only combine managers of the same resources 2017-06-01 15:34:43 -07:00
Wesley W. Terpstra
1f531b1593 tilelink2: improve round robin arbiter QoR 2017-06-01 15:34:40 -07:00
Wesley W. Terpstra
5994714970 diplomacy: move manager unification to meta-data only 
Now that PMA circuits already perform address unification, there is
no QoR gained by throwing away the true and complete diplomatic
address+node information. Defer the unification to pretty printing
the DTS address map only.
 2017-06-01 15:30:20 -07:00
Wesley W. Terpstra
0fe625c52f diplomacy: improve PMA circuit QoR 2017-06-01 15:30:20 -07:00
Henry Cook
940614625e TLCacheCork: unsafe flag now _really_ unsafe (#760) 2017-05-22 19:37:11 -07:00
Wesley W. Terpstra
7f1d3c445f Plusargs -- tilelink timeout detection from the command line (#752) 
* util: PlusArg gives Chisel access to the command-line

* tilelink2: add a progress watchdog to Monitors
 2017-05-18 22:49:59 -07:00
Wesley W. Terpstra
c8ba6b2feb unittests: accept a configurable number of transactions to run 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
f6f40b1442 unit tests: all should accept timeout override 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
8c3736e0dc tilelink2: remove ready-valid fuzzer obsoleted by TLDelayer 2017-05-17 06:47:21 -07:00
Wesley W. Terpstra
1f2236cdb3 diplomacy: appease Jack by removing unused 1st bundles argument 2017-05-17 06:46:07 -07:00
Wesley W. Terpstra
f2d16d49c2 tilelink2: don't widen TLMonitor interface unnecessarily 2017-05-17 06:29:03 -07:00
Wesley W. Terpstra
191dad7800 diplomacy: provide connect access to edges without bundles 
Forcing the bundles to exist early can mess up module ownership.
 2017-05-17 06:29:03 -07:00
Wesley W. Terpstra
3e2b477c0a rational: adjust comments and add a case for N:M 2017-05-14 15:16:33 -07:00
Wesley W. Terpstra
05e7501e7a build: include chiselName and give an example of using it (#738) 2017-05-12 06:25:58 -07:00
Henry Cook
5f3a4ada1b diplomacy: add legalize method to AddressSet 2017-05-10 12:54:24 -07:00
Henry Cook
3af40bff8b tilelink: better address masking for fuzzing 2017-05-10 12:54:24 -07:00
Wesley W. Terpstra
3eaa973da7 tilelink2: add earlyAck to regression 2017-05-09 17:35:26 -07:00
Wesley W. Terpstra
3e7bdcbf5e tilelink2: Fragmenter should ignore error when not valid 2017-05-09 17:35:26 -07:00
Wesley W. Terpstra
43c9f5fe7e tilelink2: keep earlyAck Fragmenter sources distinct 2017-05-09 17:35:22 -07:00
Wesley W. Terpstra
2d8a49cc06 tilelink2: Fragmenter client must request global FIFO 2017-05-08 00:56:45 -07:00
Wesley W. Terpstra
36f4584bb1 axi4: Test AXI4-Lite in regression 2017-05-08 00:31:35 -07:00
Wesley W. Terpstra
3209e58845 axi4: SRAM support 0 userBits 2017-05-08 00:31:14 -07:00
Wesley W. Terpstra
db76ff2d86 axi4: Deinterleaver must gather R also for single ID 
In order to guarantee that a complete R can be sent without
sinking B, the Deinterleaver must do its job even on AXI-Lite.
 2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
8fc27b0bf2 axi4: IdIndexer; a single ID does NOT imply no response interleaving 
Some slaves may never send R until you process their B.
Thus, while there is no read response interleaving, there
is still interleaving between R and B, which breaks AXI4ToTL.
 2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
4847c32599 tilelink: ToAXI4 - must interlock till last beat 
AXI4 makes no guarantee that bursts are handled atomicly.
Thus, you could be part-way through a read burst and suddenly
a write cuts ahead and is visible later, violating FIFO.
 2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
8169ba6411 axi4: IdIndexer now handles 0-width IDs 2017-05-08 00:17:02 -07:00
Scott Johnson
1cc665717d Wes fix for AXI2TL timeout when writes backed up 2017-05-04 00:54:21 -07:00
Henry Cook
1f1240baf1 fuzzer: allow fuzzing range to be overridden 2017-05-03 15:29:14 -07:00
Henry Cook
4dd3345db2 Merge branch 'master' into pipeline-mmio 2017-05-02 16:23:26 -07:00
Andrew Waterman
3a1a37d41b Support PutPartial in ScratchpadSlavePort 2017-05-02 03:07:02 -07:00
Andrew Waterman
938b089543 Remove legacy devices that use AMOALU 
I'm going to change the AMOALU API, and so I'm removing dependent dead code.
 2017-05-02 03:05:41 -07:00
Andrew Waterman
044b6ed3f9 Improve logical ops in AMOALU 
As with integer ALU, shave off some muxing.
 2017-05-02 00:14:46 -07:00
Wesley W. Terpstra
fe280187a1 axi4: Fragmenter cuts all input channel readys 
AXI4 forbids any input to lead combinationally to an output.For the AXI4ToTL
direction, front-load the cuts for {AW, AR, W}.readyAXI4ToTL makes the R and
B channels irrevocable.
 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
58a4529cc5 axi4: the last missing piece for safe FIFO ordering 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
b0b5601e8d axi4: ToTL correct error handling 
If there is an illegal AWADDR = 0x2 on a 32-bit bus, remapping it
to an aligned address on the error device may make the mask
inconsistent with the address + size.
 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
661015a78d axi4: switch arbiter to round robin 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
976af7a8c7 tilelink2: better width inference for {left,right}OR 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
40f18e6e43 diplomacy: optimize IdRange overlap detection 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
6ee69454c3 tilelink2: Fragmenter now supports early Ack 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
e09fa866b7 tilelink2: FIFOFixer should NOT change client request status 
Just because some clients are not FIFO does not matter. Downstream
FIFOFixers will still present a legitimate single domain to those
client who care.
 2017-05-01 22:53:41 -07:00
Scott Johnson
b040a462c9 Wes's change to remove user bits from external AXI interface, and add 1 cycle latency to make sure external AXI is compliant 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
d27e1928dd axi4: make maxFlight a per-master parameter 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
e1a072a644 axi4: massage test cases into shape again 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
9f08c484bd tilelink2: ToAXI4 provide FIFO order semantics 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
61a6f94196 axi4: get unit tests legal again 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
24f577c156 axi4: Deinterleaver ensures R channel ID does not change till last 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
b4188ee625 axi4: ToTL supporting pipelined MMIO 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
ca2cb033cd rocketchip: fix uses of AXI4 Fragmenter 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
e100a943ea axi4: simplify Fragmenter by using user bits 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
641a4d577a tilelink2: Error device for returning errors on demand 2017-05-01 22:53:02 -07:00
Wesley W. Terpstra
a580b17ece axi4: IdIndexer => reduce number of needed ids 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
06efc01d96 axi4: an adapter to remove user bits 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
f1217519f1 axi4: RegisterRouter; concurrent response illegal in AXI 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
5163ccd11f axi4: RegisterRouter supports user bits 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
de6ea9b442 axi4: support user bits in SRAM 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
396ecacda4 AXI4: add an optional user bundle field 2017-05-01 22:53:01 -07:00
Andrew Waterman
7c70aa593e Minor stylistic and QoR improvements to PLIC 2017-04-27 19:35:20 -07:00
Andrew Waterman
2e23d46631 Use val instead of def in ECC calculations 
This allows nicer-looking code to avoid generating lots of redundant nodes.
 2017-04-26 19:35:35 -07:00
Megan Wachs
7ad4cc36f7 debug: Prevent writes to DATA/PROGBUF when busy 2017-04-26 11:11:21 -07:00
Henry Cook
60d71efa36 ahb: make hreadyout fuzzing a sram parameter 2017-04-25 11:11:31 -07:00
Henry Cook
ca435c2f40 uncore: more verbose requires 2017-04-25 11:11:31 -07:00
Wesley W. Terpstra
d0f3004097 tilelink2: help tools save some registers in the WidthWidget (#691) 2017-04-24 15:13:58 -07:00
Henry Cook
ef8a819763 Miscellaneous periphery improvements (#689) 
* fifofixer: work around zero-width wires for single source id
* periphery: sourceshrinker takes maxInFlight parameter
 2017-04-20 11:28:00 -07:00
Megan Wachs
9002e7e532 debug: Debug Module needs to handle DMI NOPs even if DTM won't send them. 2017-04-20 10:19:50 -07:00
Megan Wachs
0c013a56c0 debug: Make DMI NOPs really NOPs. 
This simplifies SW design and CDC issues.
 2017-04-20 10:19:50 -07:00
Megan Wachs
1be13d6b4c PLIC: To avoid hazard between enable -> claim, enforce concurrency=1 2017-04-19 21:37:37 -07:00
Andrew Waterman
657f4d4e0c Permit early grant acks to broadcast hub 2017-04-18 00:47:58 -07:00
Megan Wachs
af6b2d8051 debug: DATA Region has to be aligned for ld/sd to correctly detect 64-bit cores. 2017-04-17 10:28:33 -07:00
Megan Wachs
b44d5f9386 debug: correctly consider .transfer bit in COMMAND 2017-04-17 10:28:33 -07:00
Megan Wachs
79477fbea6 debug: Properly consider 'transfer' bit 2017-04-17 10:28:33 -07:00
Megan Wachs
2dc4be6294 debug: remove preexec. Simplify the state machine since you can always just 'execute' once. 2017-04-17 10:28:33 -07:00
Wesley W. Terpstra
fcf774f125 graphML: reverse interrupt arrows 2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
ba8be17c9a tilelink2: RAMModel, use CRC16 to check AMO response 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
d794218ec3 tilelink2: RAMModel now checks atomic results 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
4f0ae1eab7 tilelink2: annotate which test generates RAMModel output 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
248acbd1b4 tilelink2: add a generic TL2 atomic evaulation unit 2017-04-14 15:13:39 -07:00
Andrew Waterman
d203c4c654 Check AMO operation legality in TLB 2017-04-14 01:03:11 -07:00
Wesley W. Terpstra
1c36ab8bf7 Fragmenter: forbid multiple sink IDs 
Otherwise a slave might respond with different IDs for different
requests and the Fragmenter would violate the requirement that
control signals remain unchanged for a burst.
 2017-04-11 12:38:00 -07:00
Wesley W. Terpstra
84dc2ae822 CacheCork: remove probe support 2017-04-11 12:34:18 -07:00
Wesley W. Terpstra
71bf929505 maskgen: support wider granularity result (#665) 
Sometimes it is useful to generate a mask with bits that correspond
to a larger unit than bytes.
 2017-04-09 20:06:23 -07:00
Megan Wachs
051acee76c Debug: Fix off-by-1 for detecting nonexistent harts. 2017-04-07 16:47:16 -07:00
Megan Wachs
01372e1686 use Wire() correctly to assign a value 2017-04-07 16:47:16 -07:00
Megan Wachs
22c6f728c3 debug: Use flags for resume instead of program buffer. Untested. 2017-04-07 16:47:16 -07:00
Megan Wachs
d361e9e343 debug: temporarily leave preexec in place 2017-04-07 16:47:16 -07:00
Megan Wachs
0e2c34b0d6 debug: update register map with new spec 2017-04-07 16:47:16 -07:00
Megan Wachs
df5caba7bf debug: Make it easier to override parts of the Default Debug Config (#655) 
* Handle single-step with a pipeline stall, not a flush

The pipeline flush approach broke when I changed the pipeline stage
the flush happens from

* debug: Make it easier to override parts of the Default Debug Config

* Fix typo in Debug code generation

abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
 2017-04-06 10:33:17 -07:00
Megan Wachs
2601740542 debug: fix some typos related to the ID->SEL mapping functions 2017-04-05 15:14:32 -07:00
Megan Wachs
b94f1f15b0 debug: redirect DMI NOPs to CONTROL register so things don't hang during reset 2017-04-05 15:14:32 -07:00
Megan Wachs
eef05cc1fc debug: Enforce mapping between hartsel and hartid, use more reasonable defaults for DATA and PROGBUF sizes. 2017-04-05 15:14:32 -07:00
Megan Wachs
629e9a2ef6 debug: Put DebugROM back inside the overall Debug Module (#647) 2017-04-03 16:36:53 -07:00
Megan Wachs
d2c1bdc2ce Debug Controls (#639) 
* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.

* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
 2017-04-03 13:31:35 -07:00
Megan Wachs
375a039279 debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec) 2017-03-28 21:14:22 -07:00
Megan Wachs
42ca597478 debug: Breaking change until FESVR is updated as well. 
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
  Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
 2017-03-27 21:19:08 -07:00
Megan Wachs
43804726ac tilelink2: more helpful requirement message 2017-03-27 21:05:05 -07:00
Megan Wachs
0c3d85b52b debug: add generated ROM contents and register fields. 2017-03-27 21:01:36 -07:00