riscv/rocket-chip
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rocket-chip/src/main/scala/uncore
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Wesley W. Terpstra db76ff2d86 axi4: Deinterleaver must gather R also for single ID 
In order to guarantee that a complete R can be sent without
sinking B, the Deinterleaver must do its job even on AXI-Lite.
2017-05-08 00:17:06 -07:00
..
agents
Heterogeneous Tiles (#550)
2017-02-09 13:59:09 -08:00
ahb
ahb: make hreadyout fuzzing a sram parameter
2017-04-25 11:11:31 -07:00
apb
apb: put both aFlow options under regression
2017-03-16 15:36:14 -07:00
axi4
axi4: Deinterleaver must gather R also for single ID
2017-05-08 00:17:06 -07:00
coherence
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
converters
Remove legacy devices that use AMOALU
2017-05-02 03:05:41 -07:00
devices
Remove legacy devices that use AMOALU
2017-05-02 03:05:41 -07:00
tilelink
Refactor Tile to use cake pattern (#502)
2017-01-16 18:24:08 -08:00
tilelink2
tilelink: ToAXI4 - must interlock till last beat
2017-05-08 00:17:06 -07:00
util
Support PutPartial in ScratchpadSlavePort
2017-05-02 03:07:02 -07:00
Consts.scala
Support PutPartial in ScratchpadSlavePort
2017-05-02 03:07:02 -07:00
Package.scala
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00