dcfbdabe60
CacheCork: better document edge conditions
2018-02-15 19:14:30 -08:00
ecd069dca4
tilelink: allow FIFO caches
...
Probably not a smart thing to build, but not illegal!
2018-02-15 19:09:37 -08:00
acecc407a5
HellaCache: we do NOT really support probe below the block size!
...
If we did, you would somehow have to retain ownership of the
unprobed parts of the block, in case they happened to be dirty.
2018-02-15 19:08:43 -08:00
fa412246b3
Error: don't be an exception wrt. caching
...
Prior to this PR, the error device was allowed to be cached by
multiple actors despite never probing any of them. This is a
pretty unusual set of properties that has caused us trouble
several times now in the past.
Let's instead put the Error device into one of two very well
established categories: a straight-up MMIO device or a tracked
memory region.
2018-02-14 23:02:55 -08:00
de91672e9a
RegFieldDesc: simplify the output RegFieldDesc JSON to just a list of reg fields
2018-02-12 08:32:52 -08:00
7bf0121f07
PLIC: correct some descriptions
2018-02-12 08:31:29 -08:00
08acbe1a29
RegFieldDesc: Clean up both descriptions and JSON presentations
2018-02-11 23:57:57 -08:00
5ab4204e8a
RegField: the JSON will just leave things out of type None
2018-02-11 22:51:36 -08:00
3b44f380d8
TLRegMapper: emit a JSON file describing the register fields
2018-02-11 22:51:36 -08:00
256f8ffc6b
Clint: Annotate regmap with RegFieldDesc
2018-02-11 21:33:09 -08:00
718c88a8f9
PLIC: Annotate regmap with RegFieldDescs
2018-02-11 21:05:17 -08:00
13b120fb01
Debug: Annotate regmaps with RegFieldDescs
2018-02-10 20:11:24 -08:00
7abf6e1c8a
RegMapper: Update cover props to use new RegFieldDesc objects
2018-02-10 13:17:38 -08:00
4ab1585a78
Register Field: Add a more verbose description object
...
Add versions of the RegField functions to take it in, and
update Example device to use it.
2018-02-10 13:17:18 -08:00
fe277cf6f0
Merge branch 'master' into auto-plusargs
2018-02-06 18:38:44 -08:00
9f6d586e8c
Add PLIC covers ( #1229 )
...
* Add another FPU hazard cover
* Add some PLIC covers
2018-02-06 17:33:33 -08:00
efc6c9cbd3
Let user of CSRFile decide when to set tval
...
I also renamed badaddr to tval (the correct name).
2018-02-06 14:05:03 -08:00
a59fc3bdaa
Teach MulDiv to do either mul-only or div-only by setting unroll=0
2018-02-06 14:03:17 -08:00
69441930b5
Rationalize ALU function encoding
...
MULHSU and MULHU should match their ISA funct3 encodings to slightly
reduce HW cost.
2018-02-06 14:00:37 -08:00
5294523551
Keep io.cpu.s1_data for visibility ( #1218 )
2018-01-31 14:31:42 -08:00
7dad486707
util: updates to internal Generator API
2018-01-30 15:19:37 -08:00
bd50a1a4bc
config: remove deprecated Parameters.root
2018-01-30 11:52:44 -08:00
46751bedeb
config: MapParameters are back in style
2018-01-30 11:52:44 -08:00
f4853c4f63
Add cover properties to Core CSRs ( #1212 )
2018-01-30 00:01:19 -08:00
b5ff853e86
Sign-extend the depc CSR ( #1209 )
2018-01-26 12:07:33 -08:00
8d8e4e1399
Merge pull request #1196 from freechipsproject/interrupt-cover
...
Cover all exceptions and interrupts
2018-01-25 18:06:13 -08:00
d2399b6d0e
Cover all exceptions and interrupts
2018-01-25 16:14:56 -08:00
a749326deb
Add cover points to registers ( #1208 )
2018-01-24 21:37:24 -08:00
7a0252fdfc
Add some covers for FPU structural hazards
2018-01-23 16:32:03 -08:00
a2ca82f92c
Add VM covers
2018-01-23 16:13:35 -08:00
c32150b994
ResetCatchAndSync: work also in the context of a RawModule ( #1202 )
2018-01-19 19:45:52 -08:00
f6f5606f8e
diplomacy: run user instantiate() method after nodes are initialized ( #1198 )
2018-01-18 14:57:47 -08:00
5cc1411e14
Merge pull request #1199 from freechipsproject/require-messages
...
rocket: add address to tlb permissions require msgs
2018-01-18 14:53:25 -08:00
bf5dd6dac3
Replace Parameters in cover with globally setable implementation ( #1200 )
...
This change is made in anticipation of a proper coverage library
2018-01-18 14:45:36 -08:00
24c1235500
rocket: add address to tlb permissions require msgs
2018-01-18 10:31:51 -08:00
5854fb5f7c
SourceShrinker improvements ( #1197 )
...
* SourceShrinker: preserve FIFO guarantees of slaves
* tilelink: document that Releases can use TtoT, BtoB, and NtoN
TtoT is needed for write-through caches.
2018-01-17 18:02:19 -08:00
338e453a91
JTAG: Use new withClock way of overriding clocks ( #1072 )
...
* JTAG: Use new withClock way of overriding clocks
the override clock way is deprecated
* JTAG: use withClock instead of override clock
* JTAG: extend Module for ClockedCounter
* JTAG: Don't use deprecated clock constructs
* JTAG: Remove another override_clock
* Rename "NegativeEdgeLatch"
because it's not a latch, it's just a register on the negative edge of the clock.
* Use the appropriately named NegEdgeReg
* JTAG: Rename another NegativeEdgeLatch
2018-01-17 13:59:05 -08:00
355d3b15e8
Merge 'origin/master' into auto-plusargs
2018-01-16 15:45:53 -05:00
80ca018e3a
Add cover points for BusErrorUnit ( #1193 )
2018-01-15 18:00:29 -08:00
04af785a5f
Emit plusArgs for unit tests
...
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com >
2018-01-15 17:54:40 -05:00
09c1d034fa
Explicitly name PlusArg serializers as *_cHeader
...
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com >
2018-01-15 17:00:12 -05:00
cfd49f87c1
Use longname for ElaborationArtefact emission
...
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com >
2018-01-15 16:55:13 -05:00
e52d52ae99
Link PlusArg to emulator command line options
...
- adds a mutable singleton (PlusArgArtefacts) to store information
about Rocket PlusArgs
- adds methods to PlusArgArtefacts to emit C snippets that are
consumed by emulator.cc for correct argument parsing and help text
generation
- emits snippets in $(CONFIG).plusArgs via BaseCoreplex-set
ElaborationArtefacts
- modify emulator/Makefrag-verilator to include $(CONFIG).plusArgs
- cleanup help text (docstring) for existing PlusArgs
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com >
2018-01-15 14:32:55 -05:00
5fe0bb0d6a
Merge remote-tracking branch 'origin/master' into refactored_rbb
2018-01-09 21:34:14 -08:00
f5211765e9
Merge pull request #1177 from freechipsproject/dont-touch-2
...
Make more use of chisel3.experimental.DontTouch
2018-01-09 15:13:55 -08:00
c152962642
Dual-port RAM replaced with single-port RAM for tag_array in HellaCache ( #1181 )
...
In accordance with https://github.com/freechipsproject/chisel3/issues/752
2018-01-09 13:06:43 -08:00
15c54b1c5a
tile: intSinkNode belongs in HasExternalInterrupts
2018-01-08 19:38:10 -08:00
11e5b620f8
tile: disable more monitors on slave port
2018-01-08 18:42:25 -08:00
5075a93e6c
util: dontTouch work-around for zero width aggregates
2018-01-08 15:58:28 -08:00
7fc8337cdb
Merge pull request #1180 from freechipsproject/addrwregdesc
...
Allow rwReg to pass name and description to RegField for documentation.
2018-01-08 09:44:44 -08:00
